diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg
index 36fe9aeda80af47f3a667f06552dea6eee0f0886..182c406f0ad1d02b54d77c3cd818a6f00868ac9d 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg
@@ -20,6 +20,9 @@ synth_files =
test_bench_files =
tb_apertif_unb1_fn_beamformer_trans.vhd
+regression_test_vhdl =
+ tb_apertif_unb1_fn_beamformer_trans.vhd
+
[modelsim_project_file]
modelsim_copy_files = ../../src/hex hex
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/tb_apertif_unb1_fn_beamformer_trans.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/tb_apertif_unb1_fn_beamformer_trans.vhd
index ae7080a4436e998398c536c2053f5731878663dd..4794877cbdc4876ebcf9fac555b9a73054c39b97 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/tb_apertif_unb1_fn_beamformer_trans.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/tb_apertif_unb1_fn_beamformer_trans.vhd
@@ -55,13 +55,17 @@ ARCHITECTURE tb OF tb_apertif_unb1_fn_beamformer_trans IS
CONSTANT c_cable_delay : TIME := 12 ns;
CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
CONSTANT c_sa_clk_period : TIME := 6.4 ns;
- CONSTANT c_clk_period : TIME := 5 ns;
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
CONSTANT c_pps_period : NATURAL := 1000;
CONSTANT c_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+
-- DUT
- SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL ext_clk : STD_LOGIC := '0';
SIGNAL pps : STD_LOGIC := '0';
SIGNAL pps_rst : STD_LOGIC := '0';
SIGNAL sa_clk : STD_LOGIC := '1';
@@ -94,7 +98,7 @@ BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
sa_clk <= NOT sa_clk AFTER c_sa_clk_period/2;
sb_clk <= NOT sb_clk AFTER c_sa_clk_period/2;
@@ -108,59 +112,59 @@ BEGIN
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
- proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+ proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_apertif_unb1_fn_beamformer : ENTITY work.apertif_unb1_fn_beamformer_transpose
- GENERIC MAP (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_nof_block_per_sync => 32 -- multiple of 16 and << HW default, to be able to load tb in sim memory
- )
- PORT MAP (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => sa_clk, -- : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
- SB_CLK => sb_clk,
-
- -- Mesh Serial I/O
- FN_BN_0_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- FN_BN_1_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- FN_BN_2_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- FN_BN_3_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
-
- -- Serial I/O
- SI_FN_0_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_1_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_2_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_3_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-
- MB_I_in => phy_in,
- MB_I_io => phy_io,
- MB_I_ou => phy_ou
- );
+ GENERIC MAP (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_nof_block_per_sync => 32 -- multiple of 16 and << HW default, to be able to load tb in sim memory
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk, -- : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
+ SB_CLK => sb_clk,
+
+ -- Mesh Serial I/O
+ FN_BN_0_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ FN_BN_1_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ FN_BN_2_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ FN_BN_3_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+
+ -- Serial I/O
+ SI_FN_0_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_3_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
+ MB_I_in => phy_in,
+ MB_I_io => phy_io,
+ MB_I_ou => phy_ou
+ );
------------------------------------------------------------------------------
-- DDR3 memory model
@@ -175,5 +179,12 @@ BEGIN
mem3_ou => phy_in
);
+ ------------------------------------------------------------------------------
+ -- Check that design can simulate some us without error
+ ------------------------------------------------------------------------------
+ sim_done <= '0', '1' AFTER 1 us;
+
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+
END tb;