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Commit 3870acad authored by Eric Kooistra's avatar Eric Kooistra
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Defined c_ctrl_address_w and c_ctlr_data_w. Corrected soft_reset_n<='1'. Renamed record fields.

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libraries/technology/ddr/tech_ddr_stratixiv.vhd
+ 37
− 26
View file @ 3870acad
...@@ -24,10 +24,10 @@ ...@@ -24,10 +24,10 @@
LIBRARY ip_stratixiv_ddr3_uphy_4g_800_master_lib; LIBRARY ip_stratixiv_ddr3_uphy_4g_800_master_lib;
LIBRARY ip_stratixiv_ddr3_uphy_4g_800_slave_lib; LIBRARY ip_stratixiv_ddr3_uphy_4g_800_slave_lib;
LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib; LIBRARY IEEE, technology_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE technology_lib.technology_pkg.ALL; USE technology_lib.technology_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL; USE work.tech_ddr_pkg.ALL;
USE work.tech_ddr_component_pkg.ALL; USE work.tech_ddr_component_pkg.ALL;
ENTITY tech_ddr_stratixiv IS ENTITY tech_ddr_stratixiv IS
...@@ -60,27 +60,36 @@ END tech_ddr_stratixiv; ...@@ -60,27 +60,36 @@ END tech_ddr_stratixiv;
ARCHITECTURE str OF tech_ddr_stratixiv IS ARCHITECTURE str OF tech_ddr_stratixiv IS
CONSTANT c_gigabytes : NATURAL := func_tech_ddr_module_size(g_tech_ddr) CONSTANT c_gigabytes : NATURAL := func_tech_ddr_module_size(g_tech_ddr);
CONSTANT c_ctrl_address_w : NATURAL := func_tech_ddr_ctrl_address_w(g_tech_ddr);
CONSTANT c_ctlr_data_w : NATURAL := func_tech_ddr_ctrl_data_w( g_tech_ddr);
SIGNAL dbg_c_gigabytes : NATURAL := c_gigabytes;
SIGNAL ctlr_ref_rst_n : STD_LOGIC;
SIGNAL ctlr_gen_rst_n : STD_LOGIC;
SIGNAL i_ctlr_gen_rst : STD_LOGIC; SIGNAL i_ctlr_gen_rst : STD_LOGIC;
SIGNAL i_ctlr_gen_clk_2x : STD_LOGIC; SIGNAL i_ctlr_gen_clk_2x : STD_LOGIC;
BEGIN BEGIN
ctlr_ref_rst_n <= NOT ctlr_ref_rst;
gen_ip_stratixiv_ddr3_uphy_4g_800_master : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=TRUE GENERATE gen_ip_stratixiv_ddr3_uphy_4g_800_master : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=TRUE GENERATE
u_ip_stratixiv_ddr3_uphy_4g_800_master : ip_stratixiv_ddr3_uphy_4g_800_master u_ip_stratixiv_ddr3_uphy_4g_800_master : ip_stratixiv_ddr3_uphy_4g_800_master
PORT MAP ( PORT MAP (
pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
global_reset_n => ctlr_ref_rst, -- global_reset.reset_n global_reset_n => ctlr_ref_rst_n, -- global_reset.reset_n
soft_reset_n => '0', -- soft_reset.reset_n soft_reset_n => '1', -- soft_reset.reset_n
afi_clk => ctlr_gen_clk, -- afi_clk.clk afi_clk => ctlr_gen_clk, -- afi_clk.clk
afi_half_clk => OPEN, -- afi_half_clk.clk afi_half_clk => OPEN, -- afi_half_clk.clk
afi_reset_n => ctlr_gen_rst, -- afi_reset.reset_n afi_reset_n => ctlr_gen_rst_n, -- afi_reset.reset_n
mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- memory.mem_a mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- memory.mem_a
mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
mem_ck => phy_io.clk(g_tech_ddr.clk_w-1 DOWNTO 0), -- .mem_ck mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck
mem_ck_n => phy_io.clk_n(g_tech_ddr.clk_w-1 DOWNTO 0), -- .mem_ck_n mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
mem_cke => phy_ou.cke(g_tech_ddr.clk_w-1 DOWNTO 0), -- .mem_cke mem_cke => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke
mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
mem_dm => phy_ou.dm(g_tech_ddr.dm_w-1 DOWNTO 0), -- .mem_dm mem_dm => phy_ou.dm(g_tech_ddr.dm_w-1 DOWNTO 0), -- .mem_dm
mem_ras_n => phy_ou.ras_n, -- .mem_ras_n mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
...@@ -90,13 +99,13 @@ BEGIN ...@@ -90,13 +99,13 @@ BEGIN
mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
mem_odt => phy_ou.odt(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_odt mem_odt => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt
avl_ready => ctrl_miso.waitrequest_n, -- avl.waitrequest_n avl_ready => ctrl_miso.waitrequest_n, -- avl.waitrequest_n
avl_burstbegin => ctrl_mosi.burstbegin, -- .beginbursttransfer avl_burstbegin => ctrl_mosi.burstbegin, -- .beginbursttransfer
avl_addr => ctrl_mosi.address(g_tech_ddr.address_w-1 DOWNTO 0), -- .address avl_addr => ctrl_mosi.address(c_ctrl_address_w-1 DOWNTO 0), -- .address
avl_rdata_valid => ctrl_miso.rdval, -- .readdatavalid avl_rdata_valid => ctrl_miso.rdval, -- .readdatavalid
avl_rdata => ctrl_miso.rddata(g_tech_ddr.data_w-1 DOWNTO 0), -- .readdata avl_rdata => ctrl_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
avl_wdata => ctrl_mosi.wrdata(g_tech_ddr.data_w-1 DOWNTO 0), -- .writedata avl_wdata => ctrl_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
avl_be => (OTHERS=>'1'), -- .byteenable avl_be => (OTHERS=>'1'), -- .byteenable
avl_read_req => ctrl_mosi.rd, -- .read avl_read_req => ctrl_mosi.rd, -- .read
avl_write_req => ctrl_mosi.wr, -- .write avl_write_req => ctrl_mosi.wr, -- .write
...@@ -123,16 +132,16 @@ BEGIN ...@@ -123,16 +132,16 @@ BEGIN
u_ip_stratixiv_ddr3_uphy_4g_800_slave : ip_stratixiv_ddr3_uphy_4g_800_slave u_ip_stratixiv_ddr3_uphy_4g_800_slave : ip_stratixiv_ddr3_uphy_4g_800_slave
PORT MAP ( PORT MAP (
pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
global_reset_n => ctlr_ref_rst, -- global_reset.reset_n global_reset_n => ctlr_ref_rst_n, -- global_reset.reset_n
soft_reset_n => '0', -- soft_reset.reset_n soft_reset_n => '1', -- soft_reset.reset_n
afi_clk => ctlr_gen_clk, -- afi_clk.clk afi_clk => ctlr_gen_clk, -- afi_clk.clk
afi_half_clk => OPEN, -- afi_half_clk.clk afi_half_clk => OPEN, -- afi_half_clk.clk
afi_reset_n => ctlr_gen_rst, -- afi_reset.reset_n afi_reset_n => ctlr_gen_rst_n, -- afi_reset.reset_n
mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- memory.mem_a mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- memory.mem_a
mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
mem_ck => phy_io.clk(g_tech_ddr.clk_w-1 DOWNTO 0), -- .mem_ck mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck
mem_ck_n => phy_io.clk_n(g_tech_ddr.clk_w-1 DOWNTO 0), -- .mem_ck_n mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
mem_cke => phy_ou.cke(g_tech_ddr.clk_w-1 DOWNTO 0), -- .mem_cke mem_cke => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke
mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
mem_dm => phy_ou.dm(g_tech_ddr.dm_w-1 DOWNTO 0), -- .mem_dm mem_dm => phy_ou.dm(g_tech_ddr.dm_w-1 DOWNTO 0), -- .mem_dm
mem_ras_n => phy_ou.ras_n, -- .mem_ras_n mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
...@@ -142,13 +151,13 @@ BEGIN ...@@ -142,13 +151,13 @@ BEGIN
mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
mem_odt => phy_ou.odt(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_odt mem_odt => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt
avl_ready => ctrl_miso.waitrequest_n, -- avl.waitrequest_n avl_ready => ctrl_miso.waitrequest_n, -- avl.waitrequest_n
avl_burstbegin => ctrl_mosi.burstbegin, -- .beginbursttransfer avl_burstbegin => ctrl_mosi.burstbegin, -- .beginbursttransfer
avl_addr => ctrl_mosi.address(g_tech_ddr.address_w-1 DOWNTO 0), -- .address avl_addr => ctrl_mosi.address(c_ctrl_address_w-1 DOWNTO 0), -- .address
avl_rdata_valid => ctrl_miso.rdval, -- .readdatavalid avl_rdata_valid => ctrl_miso.rdval, -- .readdatavalid
avl_rdata => ctrl_miso.rddata(g_tech_ddr.data_w-1 DOWNTO 0), -- .readdata avl_rdata => ctrl_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
avl_wdata => ctrl_mosi.wrdata(g_tech_ddr.data_w-1 DOWNTO 0), -- .writedata avl_wdata => ctrl_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
avl_be => (OTHERS=>'1'), -- .byteenable avl_be => (OTHERS=>'1'), -- .byteenable
avl_read_req => ctrl_mosi.rd, -- .read avl_read_req => ctrl_mosi.rd, -- .read
avl_write_req => ctrl_mosi.wr, -- .write avl_write_req => ctrl_mosi.wr, -- .write
...@@ -169,9 +178,8 @@ BEGIN ...@@ -169,9 +178,8 @@ BEGIN
); );
END GENERATE; END GENERATE;
ctlr_gen_rst <= i_ctlr_gen_rst; i_ctlr_gen_rst <= NOT ctlr_gen_rst_n;
ctlr_gen_clk_2x <= i_ctlr_gen_clk_2x;
u_async_ctlr_gen_rst_2x: ENTITY common_lib.common_async u_async_ctlr_gen_rst_2x: ENTITY common_lib.common_async
GENERIC MAP( GENERIC MAP(
g_rst_level => '0' g_rst_level => '0'
...@@ -183,4 +191,7 @@ BEGIN ...@@ -183,4 +191,7 @@ BEGIN
dout => ctlr_gen_rst_2x dout => ctlr_gen_rst_2x
); );
ctlr_gen_rst <= i_ctlr_gen_rst;
ctlr_gen_clk_2x <= i_ctlr_gen_clk_2x;
END str; END str;
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