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Commit 379b4ad2 authored by Reinier van der Walle's avatar Reinier van der Walle
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Solved modelsim errors

parent da4bf817
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2 merge requests!100Removed text for XSub that is now written in Confluence Subband correlator...,!65Resolve L2SDP-190
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applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
+ 1
− 1
View file @ 379b4ad2
hdl_lib_name = lofar2_unb2b_ring_bsp hdl_lib_name = lofar2_unb2b_ring_bsp
hdl_library_clause_name = lofar2_unb2b_ring_bsp_lib hdl_library_clause_name = lofar2_unb2b_ring_bsp_lib
hdl_lib_uses_synth = common technology dp unb2b_board ta2_unb2b_10GbE ta2_unb2b_mm_io hdl_lib_uses_synth = common technology dp unb2b_board diag ta2_unb2b_channel_cross ta2_unb2b_10GbE ta2_unb2b_mm_io
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg hdl_lib_technology = ip_arria10_e1sg
hdl_lib_include_ip = hdl_lib_include_ip =
......
applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/freeze_wrapper.v
+ 1
− 1
View file @ 379b4ad2
...@@ -145,7 +145,7 @@ module freeze_wrapper( ...@@ -145,7 +145,7 @@ module freeze_wrapper(
input [255:0] board_kernel_register_mem_readdata, input [255:0] board_kernel_register_mem_readdata,
output [255:0] board_kernel_register_mem_writedata, output [255:0] board_kernel_register_mem_writedata,
output [31:0] board_kernel_register_mem_byteenable output [31:0] board_kernel_register_mem_byteenable
);
//======================================================= //=======================================================
// pr_region instantiation // pr_region instantiation
//======================================================= //=======================================================
......
applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/pr_region.v
+ 2
− 4
View file @ 379b4ad2
...@@ -140,10 +140,8 @@ module pr_region ( ...@@ -140,10 +140,8 @@ module pr_region (
output wire kernel_stream_src_lane_ready, output wire kernel_stream_src_lane_ready,
output wire [71:0] kernel_stream_snk_lane_data, output wire [71:0] kernel_stream_snk_lane_data,
output wire kernel_stream_snk_lane_valid, output wire kernel_stream_snk_lane_valid,
input wire kernel_stream_snk_lane_ready, input wire kernel_stream_snk_lane_ready
);
wire [11:0] kernel_system_register_mem_address; wire [11:0] kernel_system_register_mem_address;
wire kernel_system_register_mem_write; wire kernel_system_register_mem_write;
wire kernel_system_register_mem_read; wire kernel_system_register_mem_read;
......
applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+ 72
− 57
View file @ 379b4ad2
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
-- . M&C -- . M&C
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, ta2_unb2b_channel_cross, ta2_unb2b_10gbe_lib, ta2_unb2b_mm_io_lib; LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, diag_lib, ta2_unb2b_channel_cross_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_mm_io_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
...@@ -44,17 +44,18 @@ USE work.top_components_pkg.ALL; ...@@ -44,17 +44,18 @@ USE work.top_components_pkg.ALL;
ENTITY top IS ENTITY top IS
GENERIC ( GENERIC (
g_design_name : STRING := "lofar2_unb2b_ring_bsp"; g_design_name : STRING := "lofar2_unb2b_ring_bsp";
g_design_note : STRING := "UNUSED"; g_design_note : STRING := "UNUSED";
g_technology : NATURAL := c_tech_arria10_e1sg; g_technology : NATURAL := c_tech_arria10_e1sg;
g_sim : BOOLEAN := FALSE; --Overridden by TB g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0; g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0; g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_revision_id : STRING := ""; -- revision_id, commit hash (first 9 chars) or number g_revision_id : STRING := ""; -- revision_id, commit hash (first 9 chars) or number
g_factory_image : BOOLEAN := FALSE; g_factory_image : BOOLEAN := FALSE;
g_protect_addr_range: BOOLEAN := FALSE g_protect_addr_range : BOOLEAN := FALSE;
g_nof_lanes : POSITIVE := 1 -- must be in range 1 - 8
); );
PORT ( PORT (
-- GENERAL -- GENERAL
...@@ -114,10 +115,14 @@ ARCHITECTURE str OF top IS ...@@ -114,10 +115,14 @@ ARCHITECTURE str OF top IS
CONSTANT c_ring_bus_w : NATURAL := c_unb2b_board_tr_ring.bus_w; CONSTANT c_ring_bus_w : NATURAL := c_unb2b_board_tr_ring.bus_w;
CONSTANT c_nof_streams_ring : NATURAL := c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus; CONSTANT c_nof_streams_ring : NATURAL := c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus;
CONSTANT c_nof_even_ring_lanes : NATURAL := ceil_div(g_nof_lanes, 2);
CONSTANT c_nof_odd_ring_lanes : NATURAL := g_nof_lanes/2;
CONSTANT c_nof_qsfp_lanes : NATURAL := c_nof_even_ring_lanes;
-- 10GbE -- 10GbE
CONSTANT c_nof_10GbE_ring_IP : NATURAL := 8; CONSTANT c_nof_10GbE_ring_IP : NATURAL := c_nof_even_ring_lanes+c_nof_odd_ring_lanes;
CONSTANT c_nof_10GbE_qsfp_IP : NATURAL := 4; CONSTANT c_nof_10GbE_qsfp_IP : NATURAL := c_nof_qsfp_lanes;
-- Firmware version x.y -- Firmware version x.y
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1); CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M; CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
...@@ -198,6 +203,16 @@ ARCHITECTURE str OF top IS ...@@ -198,6 +203,16 @@ ARCHITECTURE str OF top IS
SIGNAL reg_remu_mosi : t_mem_mosi; SIGNAL reg_remu_mosi : t_mem_mosi;
SIGNAL reg_remu_miso : t_mem_miso; SIGNAL reg_remu_miso : t_mem_miso;
-- Remote Update
SIGNAL ram_scrap_mosi : t_mem_mosi;
SIGNAL ram_scrap_miso : t_mem_miso;
-- Block Gen
SIGNAL reg_bg_ctrl_mosi : t_mem_mosi;
SIGNAL reg_bg_ctrl_miso : t_mem_miso;
SIGNAL ram_bg_data_mosi : t_mem_mosi;
SIGNAL ram_bg_data_miso : t_mem_miso;
-- MM IO -- MM IO
SIGNAL reg_ta2_unb2b_mm_io_mosi : t_mem_mosi; SIGNAL reg_ta2_unb2b_mm_io_mosi : t_mem_mosi;
SIGNAL reg_ta2_unb2b_mm_io_miso : t_mem_miso; SIGNAL reg_ta2_unb2b_mm_io_miso : t_mem_miso;
...@@ -245,27 +260,27 @@ ARCHITECTURE str OF top IS ...@@ -245,27 +260,27 @@ ARCHITECTURE str OF top IS
SIGNAL board_kernel_irq_irq : std_logic_vector(0 downto 0); SIGNAL board_kernel_irq_irq : std_logic_vector(0 downto 0);
SIGNAL board_kernel_register_mem_address : std_logic_vector(6 downto 0); := (others => '0'); -- address SIGNAL board_kernel_register_mem_address : std_logic_vector(6 downto 0) := (others => '0'); -- address
SIGNAL board_kernel_register_mem_clken : std_logic; := '0'; -- clken SIGNAL board_kernel_register_mem_clken : std_logic := '0'; -- clken
SIGNAL board_kernel_register_mem_chipselect : std_logic; := '0'; -- chipselect SIGNAL board_kernel_register_mem_chipselect : std_logic := '0'; -- chipselect
SIGNAL board_kernel_register_mem_write : std_logic; := '0'; -- write SIGNAL board_kernel_register_mem_write : std_logic := '0'; -- write
SIGNAL board_kernel_register_mem_readdata : std_logic_vector(255 downto 0); -- readdata SIGNAL board_kernel_register_mem_readdata : std_logic_vector(255 downto 0); -- readdata
SIGNAL board_kernel_register_mem_writedata : std_logic_vector(255 downto 0); := (others => '0'); -- writedata SIGNAL board_kernel_register_mem_writedata : std_logic_vector(255 downto 0) := (others => '0'); -- writedata
SIGNAL board_kernel_register_mem_byteenable : std_logic_vector(31 downto 0); := (others => '0'); -- byteenable SIGNAL board_kernel_register_mem_byteenable : std_logic_vector(31 downto 0) := (others => '0'); -- byteenable
SIGNAL ta2_unb2b_10GbE_ring_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0); SIGNAL ta2_unb2b_10GbE_ring_src_out_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL ta2_unb2b_10GbE_ring_src_in_arr : t_dp_siso_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0); SIGNAL ta2_unb2b_10GbE_ring_src_in_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL ta2_unb2b_10GbE_ring_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0); SIGNAL ta2_unb2b_10GbE_ring_snk_out_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL ta2_unb2b_10GbE_ring_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0); SIGNAL ta2_unb2b_10GbE_ring_snk_in_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL ta2_unb2b_10GbE_ring_tx_serial_r : STD_LOGIC_VECTOR(c_nof_10GbE_ring_IP -1 DOWNTO 0); SIGNAL ta2_unb2b_10GbE_ring_tx_serial_r : STD_LOGIC_VECTOR(c_nof_streams_ring -1 DOWNTO 0);
SIGNAL ta2_unb2b_10GbE_ring_rx_serial_r : STD_LOGIC_VECTOR(c_nof_10GbE_ring_IP -1 DOWNTO 0); SIGNAL ta2_unb2b_10GbE_ring_rx_serial_r : STD_LOGIC_VECTOR(c_nof_streams_ring -1 DOWNTO 0);
SIGNAL ta2_unb2b_10GbE_qsfp_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0); SIGNAL ta2_unb2b_10GbE_qsfp_src_out_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL ta2_unb2b_10GbE_qsfp_src_in_arr : t_dp_siso_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0); SIGNAL ta2_unb2b_10GbE_qsfp_src_in_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL ta2_unb2b_10GbE_qsfp_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0); SIGNAL ta2_unb2b_10GbE_qsfp_snk_out_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL ta2_unb2b_10GbE_qsfp_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0); SIGNAL ta2_unb2b_10GbE_qsfp_snk_in_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL ta2_unb2b_10GbE_qsfp_tx_serial_r : STD_LOGIC_VECTOR(c_nof_10GbE_qsfp_IP -1 DOWNTO 0); SIGNAL ta2_unb2b_10GbE_qsfp_tx_serial_r : STD_LOGIC_VECTOR(c_nof_streams_qsfp -1 DOWNTO 0);
SIGNAL ta2_unb2b_10GbE_qsfp_rx_serial_r : STD_LOGIC_VECTOR(c_nof_10GbE_qsfp_IP -1 DOWNTO 0); SIGNAL ta2_unb2b_10GbE_qsfp_rx_serial_r : STD_LOGIC_VECTOR(c_nof_streams_qsfp -1 DOWNTO 0);
SIGNAL ta2_unb2b_mm_io_snk_in : t_dp_sosi; SIGNAL ta2_unb2b_mm_io_snk_in : t_dp_sosi;
SIGNAL ta2_unb2b_mm_io_snk_out : t_dp_siso; SIGNAL ta2_unb2b_mm_io_snk_out : t_dp_siso;
...@@ -285,16 +300,16 @@ ARCHITECTURE str OF top IS ...@@ -285,16 +300,16 @@ ARCHITECTURE str OF top IS
BEGIN BEGIN
ASSERT g_nof_lanes <= c_nof_streams_ring REPORT "g_nof_lanes is configured too high!" SEVERITY ERROR;
------------ ------------
-- Front IO -- Front IO
------------ ------------
-- put the QSFP_TX/RX ports into arrays -- put the QSFP_TX/RX ports into arrays
i_QSFP_RX(0) <= QSFP_0_RX; i_QSFP_RX(0) <= QSFP_0_RX;
i_QSFP_RX(1) <= QSFP_1_RX;
QSFP_0_TX <= i_QSFP_TX(0); QSFP_0_TX <= i_QSFP_TX(0);
QSFP_1_TX <= i_QSFP_TX(1);
u_unb2b_board_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io u_unb2b_board_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io
GENERIC MAP ( GENERIC MAP (
...@@ -363,13 +378,13 @@ BEGIN ...@@ -363,13 +378,13 @@ BEGIN
-- 10GbE -- 10GbE
---------- ----------
-- ring lanes in positive direction (to the right) -- ring lanes in positive direction (to the right)
FOR I IN 0 TO c_nof_pos_ring_lanes-1 GENERATE gen_even_lanes : FOR I IN 0 TO c_nof_even_ring_lanes-1 GENERATE
unb2b_board_ring_io_serial_tx_arr(I+c_ring_bus_w) <= ta2_unb2b_10GbE_ring_tx_serial_r(I*2); -- TX[0,2,4,6] -> RING_TX1[0,1,2,3] unb2b_board_ring_io_serial_tx_arr(I+c_ring_bus_w) <= ta2_unb2b_10GbE_ring_tx_serial_r(I*2); -- TX[0,2,4,6] -> RING_TX1[0,1,2,3]
ta2_unb2b_10GbE_ring_rx_serial_r(I*2) <= unb2b_board_ring_io_serial_rx_arr(I); -- RING_RX0[0,1,2,3] -> RX[0,2,4,6] ta2_unb2b_10GbE_ring_rx_serial_r(I*2) <= unb2b_board_ring_io_serial_rx_arr(I); -- RING_RX0[0,1,2,3] -> RX[0,2,4,6]
END GENERATE; END GENERATE;
-- ring lanes in negative direction (to the left) -- ring lanes in negative direction (to the left)
FOR I IN 0 TO c_nof_neg_ring_lanes-1 GENERATE gen_odd_lanes : FOR I IN 0 TO c_nof_odd_ring_lanes-1 GENERATE
unb2b_board_ring_io_serial_tx_arr(I) <= ta2_unb2b_10GbE_ring_tx_serial_r(1+I*2); -- TX[1,3,5,7] -> RING_TX0[0,1,2,3] unb2b_board_ring_io_serial_tx_arr(I) <= ta2_unb2b_10GbE_ring_tx_serial_r(1+I*2); -- TX[1,3,5,7] -> RING_TX0[0,1,2,3]
ta2_unb2b_10GbE_ring_rx_serial_r(1+I*2) <= unb2b_board_ring_io_serial_rx_arr(I); -- RINGRX1[0,1,2,3] -> RX[1,3,5,7] ta2_unb2b_10GbE_ring_rx_serial_r(1+I*2) <= unb2b_board_ring_io_serial_rx_arr(I); -- RINGRX1[0,1,2,3] -> RX[1,3,5,7]
END GENERATE; END GENERATE;
...@@ -385,21 +400,21 @@ BEGIN ...@@ -385,21 +400,21 @@ BEGIN
clk_ref_r => SA_CLK, clk_ref_r => SA_CLK,
tx_serial_r => ta2_unb2b_10GbE_ring_tx_serial_r, tx_serial_r => ta2_unb2b_10GbE_ring_tx_serial_r(c_nof_10GbE_ring_IP-1 DOWNTO 0),
rx_serial_r => ta2_unb2b_10GbE_ring_rx_serial_r, rx_serial_r => ta2_unb2b_10GbE_ring_rx_serial_r(c_nof_10GbE_ring_IP-1 DOWNTO 0),
kernel_clk => board_kernel_clk_clk, kernel_clk => board_kernel_clk_clk,
kernel_reset => i_kernel_rst, kernel_reset => i_kernel_rst,
src_out_arr => ta2_unb2b_10GbE_ring_src_out_arr, src_out_arr => ta2_unb2b_10GbE_ring_src_out_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0),
src_in_arr => ta2_unb2b_10GbE_ring_src_in_arr, src_in_arr => ta2_unb2b_10GbE_ring_src_in_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0),
snk_out_arr => ta2_unb2b_10GbE_ring_snk_out_arr, snk_out_arr => ta2_unb2b_10GbE_ring_snk_out_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0),
snk_in_arr => ta2_unb2b_10GbE_ring_snk_in_arr snk_in_arr => ta2_unb2b_10GbE_ring_snk_in_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0)
); );
-- Front QSFP 0 RX/TX 10GbE Interface -- Front QSFP 0 RX/TX 10GbE Interface
FOR I IN 0 TO c_nof_qsfp_lanes-1 GENERATE gen_qsfp_lanes : FOR I IN 0 TO c_nof_qsfp_lanes-1 GENERATE
unb2b_board_front_io_serial_tx_arr(I) <= ta2_unb2b_10GbE_qsfp_tx_serial_r(I); unb2b_board_front_io_serial_tx_arr(I) <= ta2_unb2b_10GbE_qsfp_tx_serial_r(I);
ta2_unb2b_10GbE_qsfp_rx_serial_r(I) <= unb2b_board_front_io_serial_rx_arr(I); ta2_unb2b_10GbE_qsfp_rx_serial_r(I) <= unb2b_board_front_io_serial_rx_arr(I);
END GENERATE; END GENERATE;
...@@ -415,16 +430,16 @@ BEGIN ...@@ -415,16 +430,16 @@ BEGIN
clk_ref_r => SA_CLK, clk_ref_r => SA_CLK,
tx_serial_r => ta2_unb2b_10GbE_qsfp_tx_serial_r, tx_serial_r => ta2_unb2b_10GbE_qsfp_tx_serial_r(c_nof_10GbE_qsfp_IP-1 DOWNTO 0),
rx_serial_r => ta2_unb2b_10GbE_qsfp_rx_serial_r, rx_serial_r => ta2_unb2b_10GbE_qsfp_rx_serial_r(c_nof_10GbE_qsfp_IP-1 DOWNTO 0),
kernel_clk => board_kernel_clk_clk, kernel_clk => board_kernel_clk_clk,
kernel_reset => i_kernel_rst, kernel_reset => i_kernel_rst,
src_out_arr => ta2_unb2b_10GbE_qsfp_src_out_arr, src_out_arr => ta2_unb2b_10GbE_qsfp_src_out_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0),
src_in_arr => ta2_unb2b_10GbE_qsfp_src_in_arr, src_in_arr => ta2_unb2b_10GbE_qsfp_src_in_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0),
snk_out_arr => ta2_unb2b_10GbE_qsfp_snk_out_arr, snk_out_arr => ta2_unb2b_10GbE_qsfp_snk_out_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0),
snk_in_arr => ta2_unb2b_10GbE_qsfp_snk_in_arr snk_in_arr => ta2_unb2b_10GbE_qsfp_snk_in_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0)
); );
-------------------------------------- --------------------------------------
...@@ -475,7 +490,7 @@ BEGIN ...@@ -475,7 +490,7 @@ BEGIN
kernel_src_out_arr(0) => kernel_to_lane_sosi, kernel_src_out_arr(0) => kernel_to_lane_sosi,
kernel_src_in_arr(0) => kernel_to_lane_siso, kernel_src_in_arr(0) => kernel_to_lane_siso,
kernel_snk_out_arr(0) => kernel_from_lane_siso, kernel_snk_out_arr(0) => kernel_from_lane_siso,
kernel_snk_in_arr(0) => kernel_from_lane_sosi, kernel_snk_in_arr(0) => kernel_from_lane_sosi
); );
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -900,19 +915,19 @@ BEGIN ...@@ -900,19 +915,19 @@ BEGIN
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr, reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0), reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_scrap_address_export => ram_scrap_mosi.address(0 DOWNTO 0), ram_scrap_address_export => ram_scrap_mosi.address(8 DOWNTO 0),
ram_scrap_read_export => ram_scrap_mosi.rd, ram_scrap_read_export => ram_scrap_mosi.rd,
ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w-1 DOWNTO 0), ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w-1 DOWNTO 0),
ram_scrap_write_export => ram_scrap_mosi.wr, ram_scrap_write_export => ram_scrap_mosi.wr,
ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w-1 DOWNTO 0), ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_bg_data_address_export => ram_bg_data_mosi.address(0 DOWNTO 0), ram_bg_data_address_export => ram_bg_data_mosi.address(6 DOWNTO 0),
ram_bg_data_read_export => ram_bg_data_mosi.rd, ram_bg_data_read_export => ram_bg_data_mosi.rd,
ram_bg_data_readdata_export => ram_bg_data_miso.rddata(c_word_w-1 DOWNTO 0), ram_bg_data_readdata_export => ram_bg_data_miso.rddata(c_word_w-1 DOWNTO 0),
ram_bg_data_write_export => ram_bg_data_mosi.wr, ram_bg_data_write_export => ram_bg_data_mosi.wr,
ram_bg_data_writedata_export => ram_bg_data_mosi.wrdata(c_word_w-1 DOWNTO 0), ram_bg_data_writedata_export => ram_bg_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_bg_ctrl_address_export => reg_bg_ctrl_mosi.address(0 DOWNTO 0), reg_bg_ctrl_address_export => reg_bg_ctrl_mosi.address(2 DOWNTO 0),
reg_bg_ctrl_read_export => reg_bg_ctrl_mosi.rd, reg_bg_ctrl_read_export => reg_bg_ctrl_mosi.rd,
reg_bg_ctrl_readdata_export => reg_bg_ctrl_miso.rddata(c_word_w-1 DOWNTO 0), reg_bg_ctrl_readdata_export => reg_bg_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
reg_bg_ctrl_write_export => reg_bg_ctrl_mosi.wr, reg_bg_ctrl_write_export => reg_bg_ctrl_mosi.wr,
......
applications/ta2/ip/ta2_unb2b_channel_cross/ta2_unb2b_channel_cross.vhd
+ 12
− 12
View file @ 379b4ad2
...@@ -82,24 +82,24 @@ ARCHITECTURE str OF ta2_unb2b_channel_cross IS ...@@ -82,24 +82,24 @@ ARCHITECTURE str OF ta2_unb2b_channel_cross IS
CONSTANT c_data_w : NATURAL := c_byte_w * g_nof_bytes; CONSTANT c_data_w : NATURAL := c_byte_w * g_nof_bytes;
CONSTANT c_empty_w : NATURAL := ceil_log2(g_nof_bytes); CONSTANT c_empty_w : NATURAL := ceil_log2(g_nof_bytes);
SIGNAL dp_latency_adapter_tx_snk_in_arr : t_dp_sosi_arr(g_nof_stream-1 DOWNTO 0); SIGNAL dp_latency_adapter_tx_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_latency_adapter_tx_snk_out_arr : t_dp_siso_arr(g_nof_stream-1 DOWNTO 0); SIGNAL dp_latency_adapter_tx_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_fifo_dc_rx_src_out_arr : t_dp_sosi_arr(g_nof_stream-1 DOWNTO 0); SIGNAL dp_fifo_dc_rx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_fifo_dc_rx_src_in_arr : t_dp_siso_arr(g_nof_stream-1 DOWNTO 0); SIGNAL dp_fifo_dc_rx_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_fifo_dc_tx_snk_in_arr : t_dp_sosi_arr(g_nof_stream-1 DOWNTO 0) := (OTHERS => t_dp_sosi_rst); SIGNAL dp_fifo_dc_tx_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_fifo_dc_tx_snk_out_arr : t_dp_siso_arr(g_nof_stream-1 DOWNTO 0); SIGNAL dp_fifo_dc_tx_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_latency_adapter_rx_src_out_arr : t_dp_sosi_arr(g_nof_stream-1 DOWNTO 0); SIGNAL dp_latency_adapter_rx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_latency_adapter_rx_src_in_arr : t_dp_siso_arr(g_nof_stream-1 DOWNTO 0); SIGNAL dp_latency_adapter_rx_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
BEGIN BEGIN
ASSERT g_nof_bytes <= 64 REPORT "g_nof_bytes of ta2_unb2b_channel_cross is configured higher than 64" SEVERITY ERROR; ASSERT g_nof_bytes <= 64 REPORT "g_nof_bytes of ta2_unb2b_channel_cross is configured higher than 64" SEVERITY ERROR;
gen_streams: FOR stream IN 0 TO g_nof_stream-1 GENERATE gen_streams: FOR stream IN 0 TO g_nof_streams-1 GENERATE
-- dp_snk_in -> kernel_src_out -- dp_snk_in -> kernel_src_out
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Data mapping -- Data mapping
...@@ -111,7 +111,7 @@ BEGIN ...@@ -111,7 +111,7 @@ BEGIN
END GENERATE; END GENERATE;
END GENERATE; END GENERATE;
gen_no_reverse_tx_bytes : IF NOT g_reverse_bytes GENERATE gen_no_reverse_tx_bytes : IF NOT g_reverse_bytes GENERATE
dp_fifo_dc_tx_snk_in_arr(stream).data(c_data_w-1 DOWNTO 0)) <= dp_snk_in_arr(stream).data(c_data_w-1 DOWNTO 0); dp_fifo_dc_tx_snk_in_arr(stream).data(c_data_w-1 DOWNTO 0) <= dp_snk_in_arr(stream).data(c_data_w-1 DOWNTO 0);
END GENERATE; END GENERATE;
-- Assign correct data fields to control signals. -- Assign correct data fields to control signals.
...@@ -162,7 +162,7 @@ BEGIN ...@@ -162,7 +162,7 @@ BEGIN
snk_out => dp_latency_adapter_tx_snk_out_arr(stream), snk_out => dp_latency_adapter_tx_snk_out_arr(stream),
src_out => kernel_src_out_arr(stream), src_out => kernel_src_out_arr(stream),
src_in => kernel_src_in_src_in_arr(stream) src_in => kernel_src_in_arr(stream)
); );
...@@ -180,7 +180,7 @@ BEGIN ...@@ -180,7 +180,7 @@ BEGIN
rst => kernel_reset, rst => kernel_reset,
snk_in => kernel_snk_in_arr(stream), snk_in => kernel_snk_in_arr(stream),
snk_out => kernel_src_in_arr(stream), snk_out => kernel_snk_out_arr(stream),
src_out => dp_latency_adapter_rx_src_out_arr(stream), src_out => dp_latency_adapter_rx_src_out_arr(stream),
src_in => dp_latency_adapter_rx_src_in_arr(stream) src_in => dp_latency_adapter_rx_src_in_arr(stream)
......
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