Initial commit of lofar2_unb2b_ring_bsp

applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board_spec.xml

+<?xml version="1.0"?>
+<board version="19.2" name="lofar2_unb2b_ring_bsp">
+
+  <compile name="flat" project="top" revision="flat" qsys_file="none" generic_kernel="1">
+    <generate cmd="quartus_sh -t scripts/pre_flow_pr.tcl lofar2_unb2b_ring_bsp"/>
+    <synthesize cmd="quartus_sh --flow compile top -c flat"/>
+    <auto_migrate platform_type="a10_ref" >
+      <include fixes=""/>
+      <exclude fixes="pre_skipbak,post_skipbak"/>
+    </auto_migrate>
+  </compile>
+
+  <device device_model="10ax115s2f45i2sges_dm.xml">
+    <used_resources>
+      <alms num="33433"/> <!-- (Total ALMs) - (ALMs available to kernel_system_inst) -->
+      <ffs num="133600"/>
+      <dsps num="0"/>
+      <rams num="179"/>
+    </used_resources>
+  </device>
+
+
+  <!-- Registers, 32 bit @ 100MHz -->
+  <global_mem name="REG" max_bandwidth="3200" interleaved_bytes="32">
+    <interface name="board" port="kernel_register_mem" type="slave" width="256" maxburst="1" address="0x000000000" size="0x000001000" latency_type="fixed"/>
+  </global_mem>
+
+  <channels>
+    <!-- qsfp interfaces for connecting multiple UniBoards -->
+    <interface name="board" port="kernel_stream_src_10GbE_qsfp_0" type="streamsource" width="72" chan_id="kernel_input_10GbE_qsfp_0"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_qsfp_0" type="streamsink" width="72" chan_id="kernel_output_10GbE_qsfp_0"/>
+    <interface name="board" port="kernel_stream_src_10GbE_qsfp_1" type="streamsource" width="72" chan_id="kernel_input_10GbE_qsfp_1"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_qsfp_1" type="streamsink" width="72" chan_id="kernel_output_10GbE_qsfp_1"/>
+    <interface name="board" port="kernel_stream_src_10GbE_qsfp_2" type="streamsource" width="72" chan_id="kernel_input_10GbE_qsfp_2"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_qsfp_2" type="streamsink" width="72" chan_id="kernel_output_10GbE_qsfp_2"/>
+    <interface name="board" port="kernel_stream_src_10GbE_qsfp_3" type="streamsource" width="72" chan_id="kernel_input_10GbE_qsfp_3"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_qsfp_3" type="streamsink" width="72" chan_id="kernel_output_10GbE_qsfp_3"/>
+
+    <!-- Ring interface, ring_0, 2, 4, 6 transport in positive direction (receive from left transmit to right). ring_1, 3, 5, 7 transport in negative direction -->
+    <interface name="board" port="kernel_stream_src_10GbE_ring_0" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_0"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_0" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_0"/>
+    <interface name="board" port="kernel_stream_src_10GbE_ring_1" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_1"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_1" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_1"/>
+    <interface name="board" port="kernel_stream_src_10GbE_ring_2" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_2"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_2" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_2"/>
+    <interface name="board" port="kernel_stream_src_10GbE_ring_3" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_3"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_3" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_3"/>
+    <interface name="board" port="kernel_stream_src_10GbE_ring_4" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_4"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_4" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_4"/>
+    <interface name="board" port="kernel_stream_src_10GbE_ring_5" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_5"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_5" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_5"/>
+    <interface name="board" port="kernel_stream_src_10GbE_ring_6" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_6"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_6" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_6"/>
+    <interface name="board" port="kernel_stream_src_10GbE_ring_7" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_7"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_7" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_7"/>
+
+    <!-- IO channel from/to design -->
+    <interface name="board" port="kernel_stream_src_lane" type="streamsource" width="72" chan_id="kernel_input_to_lane"/>
+    <interface name="board" port="kernel_stream_snk_lane" type="streamsink" width="72" chan_id="kernel_output_from_lane"/>
+
+    <interface name="board" port="kernel_stream_src_mm_io" type="streamsource" width="72" chan_id="kernel_input_mm"/>
+    <interface name="board" port="kernel_stream_snk_mm_io" type="streamsink" width="32" chan_id="kernel_output_mm"/>
+  </channels>
+
+  <host>
+    <kernel_config start="0x00000000" size="0x0100000"/>
+  </host>
+
+  <interfaces>
+    <interface name="board" port="kernel_cra" type="master" width="64" misc="0"/>
+    <interface name="board" port="kernel_irq" type="irq" width="1"/>
+    <kernel_clk_reset clk="board.kernel_clk" clk2x="board.kernel_clk2x" reset="board.kernel_reset"/>
+  </interfaces>
+</board>

applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/device.tcl

+# (C) 1992-2018 Intel Corporation.                            
+# Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words    
+# and logos are trademarks of Intel Corporation or its subsidiaries in the U.S.  
+# and/or other countries. Other marks and brands may be claimed as the property  
+# of others. See Trademarks on intel.com for full list of Intel trademarks or    
+# the Trademarks & Brands Names Database (if Intel) or See www.Intel.com/legal (if Altera) 
+# Your use of Intel Corporation's design tools, logic functions and other        
+# software and tools, and its AMPP partner logic functions, and any output       
+# files any of the foregoing (including device programming or simulation         
+# files), and any associated documentation or information are expressly subject  
+# to the terms and conditions of the Altera Program License Subscription         
+# Agreement, Intel MegaCore Function License Agreement, or other applicable      
+# license agreement, including, without limitation, that your use is for the     
+# sole purpose of programming logic devices manufactured by Intel and sold by    
+# Intel or its authorized distributors.  Please refer to the applicable          
+# agreement for further details.                                                 
+
+# This file contains .qsf settings that are unique to this particular device
+
+#############################################################
+# Device
+#############################################################
+set_global_assignment -name FAMILY "Arria 10"
+set_global_assignment -name DEVICE 10AX115U2F45E1SG
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.8 V"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+#set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+#set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE ANY
+#set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 4
+set_global_assignment -name ENABLE_OCT_DONE OFF
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
+#set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X1"
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQL1024
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
+
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
+#set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+#set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+#set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+#set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 1.8V
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
+#set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_12_5MHZ
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_25MHZ
+#set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
+
+set_global_assignment -name USER_START_UP_CLOCK OFF
+
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932
+
+

applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg

+hdl_lib_name = lofar2_unb2b_ring_bsp
+hdl_library_clause_name = lofar2_unb2b_ring_bsp_lib
+hdl_lib_uses_synth = common technology dp unb2b_board ta2_unb2b_10GbE ta2_unb2b_mm_io  
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+hdl_lib_include_ip = 
+
+synth_files =
+  top_components_pkg.vhd
+  ip/pr_region.v
+  ip/freeze_wrapper.v
+  top.vhd
+
+test_bench_files =     
+
+regression_test_vhdl = 
+    
+[modelsim_project_file]
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+   ./ . 
+    
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+    
+
+quartus_vhdl_files = 
+
+quartus_qip_files =
+
+quartus_ip_files = 
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+

applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/iface.ipx

+<?xml version="1.0" encoding="UTF-8"?>
+<library>
+ <!--  date: 2018.04.26.16:36:03 -->
+ <!--  generated by: ip-make-ipx -->
+ <!--  This is a toplevel .ipx file that references mulitple .iipx (intermediate-ipx) files -->
+ <!--   -->
+ <path path="hw_iface.iipx" />
+ <path path="sw_iface.iipx" />
+</library>

applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_kclk_global.ip

+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+  <ipxact:vendor>Altera OpenCL</ipxact:vendor>
+  <ipxact:library>board_kclk_global</ipxact:library>
+  <ipxact:name>board_kclk_global</ipxact:name>
+  <ipxact:version>10.0</ipxact:version>
+  <ipxact:busInterfaces>
+    <ipxact:busInterface>
+      <ipxact:name>clk</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>clk</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>s</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="clockRate" type="longint">
+          <ipxact:name>clockRate</ipxact:name>
+          <ipxact:displayName>Clock rate</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="externallyDriven" type="bit">
+          <ipxact:name>externallyDriven</ipxact:name>
+          <ipxact:displayName>Externally driven</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="ptfSchematicName" type="string">
+          <ipxact:name>ptfSchematicName</ipxact:name>
+          <ipxact:displayName>PTF schematic name</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>global_clk</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>clk</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>g</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:master></ipxact:master>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedDirectClock" type="string">
+          <ipxact:name>associatedDirectClock</ipxact:name>
+          <ipxact:displayName>Associated direct clock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="clockRate" type="longint">
+          <ipxact:name>clockRate</ipxact:name>
+          <ipxact:displayName>Clock rate</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="clockRateKnown" type="bit">
+          <ipxact:name>clockRateKnown</ipxact:name>
+          <ipxact:displayName>Clock rate known</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="externallyDriven" type="bit">
+          <ipxact:name>externallyDriven</ipxact:name>
+          <ipxact:displayName>Externally driven</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="ptfSchematicName" type="string">
+          <ipxact:name>ptfSchematicName</ipxact:name>
+          <ipxact:displayName>PTF schematic name</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+  </ipxact:busInterfaces>
+  <ipxact:model>
+    <ipxact:views>
+      <ipxact:view>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+        <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+      </ipxact:view>
+    </ipxact:views>
+    <ipxact:instantiations>
+      <ipxact:componentInstantiation>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:moduleName>global_routing_clk</ipxact:moduleName>
+        <ipxact:fileSetRef>
+          <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+        </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
+      </ipxact:componentInstantiation>
+    </ipxact:instantiations>
+    <ipxact:ports>
+      <ipxact:port>
+        <ipxact:name>s</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>g</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+    </ipxact:ports>
+  </ipxact:model>
+  <ipxact:vendorExtensions>
+    <altera:entity_info>
+      <ipxact:vendor>Altera OpenCL</ipxact:vendor>
+      <ipxact:library>board_kclk_global</ipxact:library>
+      <ipxact:name>global_routing_clk</ipxact:name>
+      <ipxact:version>10.0</ipxact:version>
+    </altera:entity_info>
+    <altera:altera_module_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="AUTO_CLK_CLOCK_RATE" type="longint">
+          <ipxact:name>AUTO_CLK_CLOCK_RATE</ipxact:name>
+          <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+          <ipxact:value>400000000</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_module_parameters>
+    <altera:altera_system_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="device" type="string">
+          <ipxact:name>device</ipxact:name>
+          <ipxact:displayName>Device</ipxact:displayName>
+          <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceFamily" type="string">
+          <ipxact:name>deviceFamily</ipxact:name>
+          <ipxact:displayName>Device family</ipxact:displayName>
+          <ipxact:value>Arria 10</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+          <ipxact:name>deviceSpeedGrade</ipxact:name>
+          <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="generationId" type="int">
+          <ipxact:name>generationId</ipxact:name>
+          <ipxact:displayName>Generation Id</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bonusData" type="string">
+          <ipxact:name>bonusData</ipxact:name>
+          <ipxact:displayName>bonusData</ipxact:displayName>
+          <ipxact:value>bonusData 
+{
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element board_kclk_global
+   {
+   }
+}
+</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+          <ipxact:name>hideFromIPCatalog</ipxact:name>
+          <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+          <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+          <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+          <ipxact:value>&lt;boundaryDefinition&gt;
+    &lt;interfaces&gt;
+        &lt;interface&gt;
+            &lt;name&gt;clk&lt;/name&gt;
+            &lt;type&gt;clock&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;s&lt;/name&gt;
+                    &lt;role&gt;clk&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;clockRate&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;externallyDriven&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;global_clk&lt;/name&gt;
+            &lt;type&gt;clock&lt;/type&gt;
+            &lt;isStart&gt;true&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;g&lt;/name&gt;
+                    &lt;role&gt;clk&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedDirectClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;clockRate&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;clockRateKnown&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;externallyDriven&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+    &lt;/interfaces&gt;
+&lt;/boundaryDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="systemInfos" type="string">
+          <ipxact:name>systemInfos</ipxact:name>
+          <ipxact:displayName>systemInfos</ipxact:displayName>
+          <ipxact:value>&lt;systemInfosDefinition&gt;
+    &lt;connPtSystemInfos&gt;
+        &lt;entry&gt;
+            &lt;key&gt;clk&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;clk&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;CLOCK_RATE&lt;/key&gt;
+                        &lt;value&gt;400000000&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/suppliedSystemInfos&gt;
+                &lt;consumedSystemInfos/&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+        &lt;entry&gt;
+            &lt;key&gt;global_clk&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;global_clk&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos/&gt;
+                &lt;consumedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;CLOCK_RATE&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/consumedSystemInfos&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+    &lt;/connPtSystemInfos&gt;
+&lt;/systemInfosDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_system_parameters>
+    <altera:altera_interface_boundary>
+      <altera:interface_mapping altera:name="clk" altera:internal="board_kclk_global.clk" altera:type="clock" altera:dir="end">
+        <altera:port_mapping altera:name="s" altera:internal="s"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="global_clk" altera:internal="board_kclk_global.global_clk" altera:type="clock" altera:dir="start">
+        <altera:port_mapping altera:name="g" altera:internal="g"></altera:port_mapping>
+      </altera:interface_mapping>
+    </altera:altera_interface_boundary>
+    <altera:altera_has_warnings>false</altera:altera_has_warnings>
+    <altera:altera_has_errors>false</altera:altera_has_errors>
+  </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file