Try xon flow control with FIFOs and MUX.

libraries/base/dp/hdllib.cfg

@@ -251,6 +251,7 @@ test_bench_files =
     tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
     tb/vhdl/tb_dp_fifo_sc.vhd
     tb/vhdl/tb_dp_fifo_to_mm.vhd
+    tb/vhdl/tb_dp_fifo_xonoff.vhd
     tb/vhdl/tb_dp_flush.vhd
     tb/vhdl/tb_dp_gap.vhd
     tb/vhdl/tb_dp_hdr_insert_remove.vhd
@@ -368,6 +369,7 @@ test_bench_files =
 
 regression_test_vhdl = 
     tb/vhdl/tb_dp_fifo_to_mm.vhd
+    tb/vhdl/tb_dp_fifo_xonoff.vhd
     tb/vhdl/tb_dp_latency_adapter.vhd
     tb/vhdl/tb_dp_shiftreg.vhd
     tb/vhdl/tb_dp_bsn_source.vhd