Corrected address and data widths

libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd

@@ -78,8 +78,7 @@ END mms_diag_wg_wideband_arr;
 
 ARCHITECTURE str OF mms_diag_wg_wideband_arr IS
 
-  CONSTANT c_reg_adr_w    : NATURAL := ceil_log2(2);
-  CONSTANT c_buf_adr_w    : NATURAL := ceil_log2(10);
+  CONSTANT c_reg_adr_w    : NATURAL := 2;
     
   SIGNAL reg_mosi_arr     : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
   SIGNAL reg_miso_arr     : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0); 
@@ -108,7 +107,7 @@ BEGIN
   u_common_mem_mux_buf : ENTITY common_lib.common_mem_mux
   GENERIC MAP (    
     g_nof_mosi    => g_nof_streams,
-    g_mult_addr_w => c_buf_adr_w
+    g_mult_addr_w => g_buf_addr_w
   )
   PORT MAP (
     mosi     => buf_mosi,

libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd

@@ -61,8 +61,8 @@ END mms_aduh_monitor_arr;
 
 ARCHITECTURE str OF mms_aduh_monitor_arr IS
 
-  CONSTANT c_reg_adr_w    : NATURAL := ceil_log2(2);
-  CONSTANT c_buf_adr_w    : NATURAL := ceil_log2(8);
+  CONSTANT c_reg_adr_w    : NATURAL := 2;
+  CONSTANT c_buf_adr_w    : NATURAL := ceil_log2(g_buffer_nof_symbols);
 
   SIGNAL reg_mosi_arr     : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
   SIGNAL reg_miso_arr     : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0);