Adjusted tb_init to make tb result passed again.

libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd

@@ -77,7 +77,7 @@ ARCHITECTURE tb OF tb_lvdsh_dd_phs4 IS
   
   CONSTANT c_sim                : BOOLEAN := TRUE;
   CONSTANT c_tb_duration        : NATURAL := sel_a_b(g_dclk_drift/=0 ps OR g_dclk_offon=TRUE, 3000, 10);   -- nof tb intervals for tb duration
-  CONSTANT c_tb_init            : NATURAL := sel_a_b(g_dclk_drift/=0 ps OR g_dclk_offon=TRUE,   10, 10);   -- nof tb intervals for tb init before verify_en
+  CONSTANT c_tb_init            : NATURAL := sel_a_b(g_dclk_drift/=0 ps OR g_dclk_offon=TRUE,   20, 20);   -- nof tb intervals for tb init before verify_en
   
   CONSTANT c_clk_factor         : NATURAL := 100;  -- slow down dclk to improve modelling dclk phase uncertainy with g_dclk_drift, which is minimal 2 ps
   CONSTANT c_ref_s_clk_period   : TIME := c_clk_factor*1.25 ns;                -- 800 MHz sample clock for dp_sample_dat monitor