From 352ccfd7db345e0658194cdf1fde464cba5fefac Mon Sep 17 00:00:00 2001 From: Erik Kooistra <kooistra@astron.nl> Date: Fri, 28 Jul 2017 08:50:19 +0000 Subject: [PATCH] Adjusted tb_init to make tb result passed again. --- libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd index 00e1771c84..1073390f69 100644 --- a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd +++ b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd @@ -77,7 +77,7 @@ ARCHITECTURE tb OF tb_lvdsh_dd_phs4 IS CONSTANT c_sim : BOOLEAN := TRUE; CONSTANT c_tb_duration : NATURAL := sel_a_b(g_dclk_drift/=0 ps OR g_dclk_offon=TRUE, 3000, 10); -- nof tb intervals for tb duration - CONSTANT c_tb_init : NATURAL := sel_a_b(g_dclk_drift/=0 ps OR g_dclk_offon=TRUE, 10, 10); -- nof tb intervals for tb init before verify_en + CONSTANT c_tb_init : NATURAL := sel_a_b(g_dclk_drift/=0 ps OR g_dclk_offon=TRUE, 20, 20); -- nof tb intervals for tb init before verify_en CONSTANT c_clk_factor : NATURAL := 100; -- slow down dclk to improve modelling dclk phase uncertainy with g_dclk_drift, which is minimal 2 ps CONSTANT c_ref_s_clk_period : TIME := c_clk_factor*1.25 ns; -- 800 MHz sample clock for dp_sample_dat monitor -- GitLab