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Commit 34eaf737 authored by Eric Kooistra's avatar Eric Kooistra
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Merge branch 'L2SDP-178' into 'master' 

Resolve L2SDP-178

Closes L2SDP-178

See merge request desp/hdl!66
parents 6648d6a3 48db35a7
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2 merge requests!100Removed text for XSub that is now written in Confluence Subband correlator...,!66Resolve L2SDP-178
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applications/lofar2/designs/lofar2_unb2b_adc/doc/README 0 → 100644
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Quick steps to compile
----------------------
-> In case of a new installation, the IP's have to be generated for Arria10.
cd ~/git/hdl
. init_hdl.sh
compile_altera_simlibs unb2b
generate_ip_libs unb2b
-> For compilation it might be necessary to check the .vhd file:
$RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
-> Make sure you have set up the RadioHDL/trunk/tools/quartus/set_quartus script correctly to use quartus 17 for unb2b.
-> Make sure you use the modified avs2_eth_coe_hw.tcl (see attachment of this e-mail), this file is placed in RadioHDL/trunk/libraries/io/eth/src/vhdl.
1. Start with the Oneclick Commands:
cd ~/git/hdl
. init_hdl.sh
quartus_config unb2b
# 2. Generate MMM for QSYS:
run_qsys_pro unb2b unb2b_minimal
3. -> From here either continue to Modelsim (simulation) or Quartus (synthesis)
applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.ip → applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_2.ip
+ 23
− 33
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<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
<ipxact:library>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd</ipxact:library>
<ipxact:name>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd</ipxact:name>
<ipxact:library>qsys_lofar2_unb2b_adc_avs_common_mm_2</ipxact:library>
<ipxact:name>avs_common_mm_2</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
......@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
<ipxact:value>262144</ipxact:value>
<ipxact:value>8</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
......@@ -664,12 +664,7 @@
<ipxact:name>avs_mem_address</ipxact:name>
<ipxact:wire>
<ipxact:direction>in</ipxact:direction>
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
<ipxact:right>15</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:vectors></ipxact:vectors>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
......@@ -770,12 +765,7 @@
<ipxact:name>coe_address_export</ipxact:name>
<ipxact:wire>
<ipxact:direction>out</ipxact:direction>
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
<ipxact:right>15</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:vectors></ipxact:vectors>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
......@@ -851,7 +841,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
<ipxact:library>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd</ipxact:library>
<ipxact:library>qsys_lofar2_unb2b_adc_avs_common_mm_2</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
......@@ -860,7 +850,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
<ipxact:value>16</ipxact:value>
<ipxact:value>1</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
......@@ -909,7 +899,7 @@
type = "String";
}
}
element ram_diag_data_buffer_jesd
element avs_common_mm_2
{
}
}
......@@ -997,7 +987,7 @@
&lt;name&gt;avs_mem_address&lt;/name&gt;
&lt;role&gt;address&lt;/role&gt;
&lt;direction&gt;Input&lt;/direction&gt;
&lt;width&gt;16&lt;/width&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
&lt;/port&gt;
......@@ -1066,7 +1056,7 @@
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;addressSpan&lt;/key&gt;
&lt;value&gt;262144&lt;/value&gt;
&lt;value&gt;8&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;addressUnits&lt;/key&gt;
......@@ -1295,7 +1285,7 @@
&lt;name&gt;coe_address_export&lt;/name&gt;
&lt;role&gt;export&lt;/role&gt;
&lt;direction&gt;Output&lt;/direction&gt;
&lt;width&gt;16&lt;/width&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
&lt;/port&gt;
......@@ -1462,11 +1452,11 @@
&lt;consumedSystemInfos&gt;
&lt;entry&gt;
&lt;key&gt;ADDRESS_MAP&lt;/key&gt;
&lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x40000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
&lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
&lt;value&gt;18&lt;/value&gt;
&lt;value&gt;3&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
......@@ -1494,38 +1484,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
<altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.address" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="address" altera:internal="avs_common_mm_2.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.clk" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="clk" altera:internal="avs_common_mm_2.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.mem" altera:type="avalon" altera:dir="end">
<altera:interface_mapping altera:name="mem" altera:internal="avs_common_mm_2.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.read" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="read" altera:internal="avs_common_mm_2.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.readdata" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="readdata" altera:internal="avs_common_mm_2.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.reset" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="reset" altera:internal="avs_common_mm_2.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.system" altera:type="clock" altera:dir="end">
<altera:interface_mapping altera:name="system" altera:internal="avs_common_mm_2.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.system_reset" altera:type="reset" altera:dir="end">
<altera:interface_mapping altera:name="system_reset" altera:internal="avs_common_mm_2.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.write" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="write" altera:internal="avs_common_mm_2.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.writedata" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="writedata" altera:internal="avs_common_mm_2.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
......
applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc
+ 3
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......@@ -50,6 +50,7 @@ create_clock -period 100Mhz [get_ports {CLKUSR}]
create_clock -period 644.53125Mhz [get_ports {SA_CLK}]
create_clock -period 644.53125Mhz [get_ports {SB_CLK}]
create_clock -period 200MHz -name {BCK_REF_CLK} { BCK_REF_CLK }
#create_clock -period 100MHz -name {BCK_REF_CLK} { BCK_REF_CLK }
derive_pll_clocks
derive_clock_uncertainty
......@@ -98,4 +99,5 @@ set_false_path -from [get_clocks {*core_pll|frame_clk}] -to [get_clocks {*xcvr_f
# Constraint on the SYSREF input pin
# Adjust this to account for any board trace difference between SYSREF and REFCLK
# See page 150: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf
set_input_delay -clock BCK_REF_CLK 0 [get_ports JESD204B_SYSREF]
applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/hdllib.cfg 0 → 100644
+ 78
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hdl_lib_name = lofar2_unb2b_adc_6ch_200MHz
hdl_library_clause_name = lofar2_unb2b_adc_6ch_200MHz_lib
hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_adc
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
lofar2_unb2b_adc_6ch_200MHz.vhd
test_bench_files =
tb_lofar2_unb2b_adc_6ch_200MHz.vhd
regression_test_vhdl =
tb_lofar2_unb2b_adc_6ch_200MHz.vhd
[modelsim_project_file]
modelsim_copy_files =
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
../../quartus .
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_files =
../../quartus/lofar2_unb2b_adc.sdc
quartus_tcl_files =
../../quartus/lofar2_unb2b_adc_pins.tcl
quartus_vhdl_files =
quartus_qip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_6ch_200MHz/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip
quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd 0 → 100644
+ 165
− 0
View file @ 34eaf737
-------------------------------------------------------------------------------
--
-- Copyright 2020
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
-- Author : J Hargreaves
-- Purpose:
-- Wrapper for full adc input test design
-- Description:
-- Unb2b version for lab testing
-- Contains complete AIT input stage with 12 ADC streams
LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
ENTITY lofar2_unb2b_adc_6ch_200MHz IS
GENERIC (
g_design_name : STRING := "lofar2_unb2b_adc_6ch_200MHz";
g_design_note : STRING := "Lofar2 with 6 ADC input streams";
g_jesd_freq : STRING := "200MHz";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_revision_id : STRING := "" -- revision ID -- set by QSF
);
PORT (
-- GENERAL
CLK : IN STD_LOGIC; -- System Clock
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
SENS_SC : INOUT STD_LOGIC;
SENS_SD : INOUT STD_LOGIC;
PMBUS_SC : INOUT STD_LOGIC;
PMBUS_SD : INOUT STD_LOGIC;
PMBUS_ALERT : IN STD_LOGIC := '0';
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
-- back transceivers (note only 6 are used in unb2b)
BCK_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
);
END lofar2_unb2b_adc_6ch_200MHz;
ARCHITECTURE str OF lofar2_unb2b_adc_6ch_200MHz IS
SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC;
BEGIN
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
JESD204B_SERIAL_DATA(6) <= '0';
JESD204B_SERIAL_DATA(7) <= '0';
JESD204B_SERIAL_DATA(8) <= '0';
JESD204B_SERIAL_DATA(9) <= '0';
JESD204B_SERIAL_DATA(10) <= '0';
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
u_revision : ENTITY lofar2_unb2b_adc_lib.lofar2_unb2b_adc
GENERIC MAP (
g_design_name => g_design_name,
g_design_note => g_design_note,
g_jesd_freq => g_jesd_freq,
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_revision_id => g_revision_id
)
PORT MAP (
-- GENERAL
CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
VERSION => VERSION,
ID => ID,
TESTIO => TESTIO,
-- I2C Interface to Sensors
SENS_SC => SENS_SC,
SENS_SD => SENS_SD,
PMBUS_SC => PMBUS_SC,
PMBUS_SD => PMBUS_SD,
PMBUS_ALERT => PMBUS_ALERT,
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT,
-- LEDs
QSFP_LED => QSFP_LED,
-- back transceivers
JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
JESD204B_REFCLK => JESD204B_REFCLK,
-- jesd204b syncronization signals
JESD204B_SYSREF => JESD204B_SYSREF,
JESD204B_SYNC_N => jesd204b_sync_n_arr
);
END str;
applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd 0 → 100644
+ 165
− 0
View file @ 34eaf737
-------------------------------------------------------------------------------
--
-- Copyright 2020
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
-- Author: Jonathan Hargreaves
-- Purpose: Tb to show that lofar2_unb2b_adc_6ch_200MHz can simulate
-- Description:
-- This is a compile-only test bench
-- Usage:
-- Load sim # check that design can load in vsim
-- > as 10 # check that the hierarchy for g_design_name is complete
-- > run -a # check that design can simulate some us without error
LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
ENTITY tb_lofar2_unb2b_adc_6ch_200MHz IS
END tb_lofar2_unb2b_adc_6ch_200MHz;
ARCHITECTURE tb OF tb_lofar2_unb2b_adc_6ch_200MHz IS
CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
CONSTANT c_node_nr : NATURAL := 0; -- Back node 3
CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_ext_clk_period : TIME := 5 ns;
CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
CONSTANT c_pps_period : NATURAL := 1000;
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL sim_done : STD_LOGIC := '0';
-- DUT
SIGNAL ext_clk : STD_LOGIC := '0';
SIGNAL pps : STD_LOGIC := '0';
SIGNAL pps_rst : STD_LOGIC := '0';
SIGNAL WDI : STD_LOGIC;
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
SIGNAL eth_clk : STD_LOGIC := '0';
SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
SIGNAL pmbus_scl : STD_LOGIC;
SIGNAL pmbus_sda : STD_LOGIC;
-- back transceivers
SIGNAL bck_rx : STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1 downto c_unb2b_board_nof_tr_jesd204b);
SIGNAL bck_ref_clk : STD_LOGIC := '1';
-- jesd204b syncronization signals
SIGNAL jesd204b_sysref : STD_LOGIC;
SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
bck_ref_clk <= NOT bck_ref_clk AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
sens_scl <= 'H'; -- pull up
sens_sda <= 'H'; -- pull up
pmbus_scl <= 'H'; -- pull up
pmbus_sda <= 'H'; -- pull up
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
jesd204b_sysref <= pps;
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc_6ch_200MHz : ENTITY work.lofar2_unb2b_adc_6ch_200MHz
GENERIC MAP (
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
g_sim_node_nr => c_node_nr
)
PORT MAP (
-- GENERAL
CLK => ext_clk,
PPS => pps,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
VERSION => c_version,
ID => c_id,
TESTIO => open,
-- I2C Interface to Sensors
SENS_SC => sens_scl,
SENS_SD => sens_sda,
PMBUS_SC => pmbus_scl,
PMBUS_SD => pmbus_sda,
PMBUS_ALERT => open,
-- 1GbE Control Interface
ETH_CLK => eth_clk,
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp,
-- LEDs
QSFP_LED => open,
-- back transceivers
BCK_RX => bck_rx,
BCK_REF_CLK => bck_ref_clk,
-- jesd204b syncronization signals
JESD204B_SYSREF => jesd204b_sysref,
JESD204B_SYNC_N => jesd204b_sync_n
);
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
sim_done <= '0', '1' AFTER 1 us;
proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
END tb;
applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
+ 1
− 4
View file @ 34eaf737
......@@ -31,10 +31,8 @@ quartus_copy_files =
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
# use lofar2_unb2b_adc.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2b_adc.sdc
#$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
../../quartus/lofar2_unb2b_adc_pins.tcl
......@@ -48,6 +46,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip
......@@ -71,14 +70,12 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
......
applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+ 43
− 21
View file @ 34eaf737
......@@ -42,6 +42,7 @@ ENTITY lofar2_unb2b_adc IS
GENERIC (
g_design_name : STRING := "lofar2_unb2b_adc";
g_design_note : STRING := "UNUSED";
g_jesd_freq : STRING := "200MHz";
g_technology : NATURAL := c_tech_arria10_e1sg;
g_buf_nof_data : NATURAL := 1024;
g_sim : BOOLEAN := FALSE; --Overridden by TB
......@@ -104,7 +105,7 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
-- Firmware version x.y
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
CONSTANT c_lofar2_sample_clk_freq : NATURAL := 200 * 10**6; -- alternate 160MHz. TODO: Use to check PPS
-- System
SIGNAL cs_sim : STD_LOGIC;
......@@ -117,6 +118,8 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
SIGNAL dp_pps : STD_LOGIC;
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC;
SIGNAL jesd_mm_rst : STD_LOGIC;
SIGNAL jesd_dp_rst : STD_LOGIC;
-- PIOs
SIGNAL pout_wdi : STD_LOGIC;
......@@ -205,12 +208,6 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
SIGNAL reg_bsn_monitor_input_mosi : t_mem_mosi;
SIGNAL reg_bsn_monitor_input_miso : t_mem_miso;
-- Data buffer raw
SIGNAL ram_diag_data_buf_jesd_mosi: t_mem_mosi;
SIGNAL ram_diag_data_buf_jesd_miso: t_mem_miso;
SIGNAL reg_diag_data_buf_jesd_mosi: t_mem_mosi;
SIGNAL reg_diag_data_buf_jesd_miso: t_mem_miso;
-- Data buffer bsn
SIGNAL ram_diag_data_buf_bsn_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_bsn_miso : t_mem_miso;
......@@ -229,7 +226,9 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
SIGNAL alt_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
-- JESD control
SIGNAL jesd_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL jesd_ctrl_miso : t_mem_miso := c_mem_miso_rst;
BEGIN
......@@ -374,6 +373,10 @@ BEGIN
-- PIOs
pout_wdi => pout_wdi,
-- Jesd reset control
jesd_ctrl_mosi => jesd_ctrl_mosi,
jesd_ctrl_miso => jesd_ctrl_miso,
-- mm interfaces for control
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
......@@ -428,10 +431,6 @@ BEGIN
ram_wg_miso => ram_wg_miso,
reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
......@@ -452,6 +451,7 @@ BEGIN
GENERIC MAP(
g_technology => g_technology,
g_nof_streams => c_nof_streams,
g_jesd_freq => g_jesd_freq,
g_sim => g_sim
)
PORT MAP(
......@@ -476,10 +476,6 @@ BEGIN
ram_wg_miso => ram_wg_miso,
reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
......@@ -488,6 +484,8 @@ BEGIN
ram_aduh_monitor_miso => ram_aduh_monitor_miso,
reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
reg_aduh_monitor_miso => reg_aduh_monitor_miso,
jesd_ctrl_mosi => jesd_ctrl_mosi,
jesd_ctrl_miso => jesd_ctrl_miso,
-- Jesd external IOs
jesd204b_serial_data => JESD204B_SERIAL_DATA,
......@@ -499,5 +497,29 @@ BEGIN
out_sosi_arr => alt_sosi_arr
);
u_front_led : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds
GENERIC MAP (
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
)
PORT MAP (
rst => mm_rst,
clk => mm_clk,
green_led_arr => qsfp_green_led_arr,
red_led_arr => qsfp_red_led_arr
);
u_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io
GENERIC MAP (
g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
)
PORT MAP (
green_led_arr => qsfp_green_led_arr,
red_led_arr => qsfp_red_led_arr,
QSFP_LED => QSFP_LED
);
END str;
applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
+ 1
− 0
View file @ 34eaf737
......@@ -53,6 +53,7 @@ PACKAGE BODY lofar2_unb2b_adc_pkg IS
BEGIN
IF g_design_name = "lofar2_unb2b_adc_one_node" THEN RETURN c_one_node;
ELSIF g_design_name = "lofar2_unb2b_adc_full" THEN RETURN c_full;
ELSIF g_design_name = "lofar2_unb2b_adc_6ch_200MHz" THEN RETURN c_full;
ELSE RETURN c_one_node;
END IF;
END;
......
applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
+ 13
− 27
View file @ 34eaf737
......@@ -103,6 +103,10 @@ ENTITY mmm_lofar2_unb2b_adc IS
jesd204b_mosi : OUT t_mem_mosi;
jesd204b_miso : IN t_mem_miso;
-- Jesd reset control
jesd_ctrl_mosi : OUT t_mem_mosi;
jesd_ctrl_miso : IN t_mem_miso;
-- Dp shiftram
reg_dp_shiftram_mosi : OUT t_mem_mosi;
reg_dp_shiftram_miso : IN t_mem_miso;
......@@ -125,12 +129,6 @@ ENTITY mmm_lofar2_unb2b_adc IS
ram_wg_mosi : OUT t_mem_mosi;
ram_wg_miso : IN t_mem_miso;
-- JESD databuffer
ram_diag_data_buf_jesd_mosi : OUT t_mem_mosi;
ram_diag_data_buf_jesd_miso : IN t_mem_miso;
reg_diag_data_buf_jesd_mosi : OUT t_mem_mosi;
reg_diag_data_buf_jesd_miso : IN t_mem_miso;
-- Bsn databuffer
ram_diag_data_buf_bsn_mosi : OUT t_mem_mosi;
ram_diag_data_buf_bsn_miso : IN t_mem_miso;
......@@ -207,11 +205,6 @@ BEGIN
u_mm_file_ram_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
PORT MAP(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
u_mm_file_ram_diag_data_buf_jesd : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
u_mm_file_reg_diag_data_buf_jesd : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
u_mm_file_ram_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
u_mm_file_reg_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
......@@ -244,6 +237,7 @@ BEGIN
-- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
pio_wdi_external_connection_export => pout_wdi,
avs_eth_0_reset_export => eth1g_mm_rst,
avs_eth_0_clk_export => OPEN,
avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
......@@ -348,6 +342,14 @@ BEGIN
jesd204b_read_export => jesd204b_mosi.rd,
jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w-1 DOWNTO 0),
pio_jesd_ctrl_reset_export => OPEN,
pio_jesd_ctrl_clk_export => OPEN,
pio_jesd_ctrl_address_export => jesd_ctrl_mosi.address(0 downto 0),
pio_jesd_ctrl_write_export => jesd_ctrl_mosi.wr,
pio_jesd_ctrl_writedata_export => jesd_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
pio_jesd_ctrl_read_export => jesd_ctrl_mosi.rd,
pio_jesd_ctrl_readdata_export => jesd_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(7 DOWNTO 0),
reg_bsn_monitor_input_clk_export => OPEN,
reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
......@@ -454,22 +456,6 @@ BEGIN
reg_diag_data_buf_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
reg_diag_data_buf_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
ram_diag_data_buf_jesd_clk_export => OPEN,
ram_diag_data_buf_jesd_reset_export => OPEN,
ram_diag_data_buf_jesd_address_export => ram_diag_data_buf_jesd_mosi.address(16-1 DOWNTO 0),
ram_diag_data_buf_jesd_write_export => ram_diag_data_buf_jesd_mosi.wr,
ram_diag_data_buf_jesd_writedata_export => ram_diag_data_buf_jesd_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buf_jesd_read_export => ram_diag_data_buf_jesd_mosi.rd,
ram_diag_data_buf_jesd_readdata_export => ram_diag_data_buf_jesd_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_data_buf_jesd_reset_export => OPEN,
reg_diag_data_buf_jesd_clk_export => OPEN,
reg_diag_data_buf_jesd_address_export => reg_diag_data_buf_jesd_mosi.address(12-1 DOWNTO 0),
reg_diag_data_buf_jesd_write_export => reg_diag_data_buf_jesd_mosi.wr,
reg_diag_data_buf_jesd_writedata_export => reg_diag_data_buf_jesd_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_data_buf_jesd_read_export => reg_diag_data_buf_jesd_mosi.rd,
reg_diag_data_buf_jesd_readdata_export => reg_diag_data_buf_jesd_miso.rddata(c_word_w-1 DOWNTO 0),
ram_aduh_monitor_clk_export => OPEN,
ram_aduh_monitor_reset_export => OPEN,
ram_aduh_monitor_address_export => ram_aduh_monitor_mosi.address(12-1 DOWNTO 0),
......
applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+ 66
− 54
View file @ 34eaf737
......@@ -18,7 +18,7 @@
--
-------------------------------------------------------------------------------
-- Author : J Hargreaves
-- Authors : J Hargreaves, L Hiemstra
-- Purpose:
-- AIT - ADC (Jesd) receiver, input, timing and associated diagnostic blocks
-- Description:
......@@ -41,6 +41,7 @@ USE work.lofar2_unb2b_adc_pkg.ALL;
ENTITY node_adc_input_and_timing IS
GENERIC (
g_technology : NATURAL := c_tech_arria10_e1sg;
g_jesd_freq : STRING := "200MHz";
g_buf_nof_data : NATURAL := 131072; --8192; --1024;
g_nof_streams : NATURAL := 12;
g_nof_sync_n : NATURAL := 4; -- Three ADCs per RCU share a sync
......@@ -55,6 +56,7 @@ ENTITY node_adc_input_and_timing IS
dp_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
-- mm control buses
-- JESD
jesd204b_mosi : IN t_mem_mosi := c_mem_mosi_rst;
......@@ -100,6 +102,10 @@ ENTITY node_adc_input_and_timing IS
reg_aduh_monitor_mosi : IN t_mem_mosi;
reg_aduh_monitor_miso : OUT t_mem_miso;
-- JESD control
jesd_ctrl_mosi : IN t_mem_mosi;
jesd_ctrl_miso : OUT t_mem_miso;
-- JESD io signals
jesd204b_serial_data : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
jesd204b_refclk : IN STD_LOGIC;
......@@ -115,13 +121,13 @@ END node_adc_input_and_timing;
ARCHITECTURE str OF node_adc_input_and_timing IS
-- Firmware version x.y
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
CONSTANT c_lofar2_sample_clk_freq : NATURAL := 200 * 10**6; -- alternate 160MHz. TODO: Use to check PPS
CONSTANT c_nof_streams_jesd204b : NATURAL := 12; -- IP is set up for 12 streams
CONSTANT c_nof_streams_db : NATURAL := 2; -- Streams of raw samples to record in db
CONSTANT c_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
adr_w => 1,
dat_w => c_word_w,
nof_dat => 1,
init_sl => '0');
-- Waveform Generator
CONSTANT c_wg_buf_directory : STRING := "data/";
......@@ -155,16 +161,32 @@ ARCHITECTURE str OF node_adc_input_and_timing IS
SIGNAL rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
SIGNAL dp_shiftram_snk_in_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
SIGNAL ant_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(c_nof_streams_db-1 DOWNTO 0);
SIGNAL bs_sosi : t_dp_sosi;
SIGNAL wg_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL mux_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL nxt_mux_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL st_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL mm_rst_internal : STD_LOGIC;
SIGNAL mm_jesd_ctrl_reg : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL jesd204b_disable_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL jesd204b_reset : STD_LOGIC;
BEGIN
-- The node AIT is reset at power up by mm_rst and under software control by jesd204b_reset.
-- The mm_rst internal will cause a reset on the rx_rst by the reset sequencer in the u_jesd204b.
-- The MM jesd204b_reset is intended for node AIT resynchronisation tests of the u_jesd204b.
-- The MM jesd204b_reset should not be applied in an SDP application, because this will cause
-- a disturbance in the block timing of the out_sosi_arr(i).sync,bsn,sop,eop. The other logic
-- in an SDP application assumes that the block timing of the out_sosi_arr(i) only contains
-- complete blocks, so from sop to eop.
mm_rst_internal <= mm_rst OR mm_jesd_ctrl_reg(31);
gen_jesd_disable : FOR I IN 0 TO c_nof_streams_jesd204b-1 GENERATE
jesd204b_disable_arr(i) <= mm_jesd_ctrl_reg(i);
END GENERATE;
-----------------------------------------------------------------------------
-- JESD204B IP (ADC Handler)
-----------------------------------------------------------------------------
......@@ -173,7 +195,8 @@ BEGIN
GENERIC MAP(
g_sim => g_sim,
g_nof_streams => c_nof_streams_jesd204b,
g_nof_sync_n => g_nof_sync_n
g_nof_sync_n => g_nof_sync_n,
g_jesd_freq => g_jesd_freq
)
PORT MAP(
jesd204b_refclk => JESD204B_REFCLK,
......@@ -185,9 +208,11 @@ BEGIN
rx_rst => rx_rst,
rx_sysref => rx_sysref,
jesd204b_disable_arr => jesd204b_disable_arr,
-- MM
mm_clk => mm_clk,
mm_rst => mm_rst,
mm_rst => mm_rst_internal,
jesd204b_mosi => jesd204b_mosi,
jesd204b_miso => jesd204b_miso,
......@@ -198,43 +223,6 @@ BEGIN
);
gen_jesd_mon_in : FOR i IN 0 TO c_nof_streams_db-1 GENERATE
diag_data_buf_snk_in_arr(i).data(c_data_w-1 downto 0) <= rx_sosi_arr(i).data(c_data_w-1 downto 0);
diag_data_buf_snk_in_arr(i).valid <= rx_sosi_arr(i).valid;
diag_data_buf_snk_in_arr(i).sop <= '0';
diag_data_buf_snk_in_arr(i).eop <= '0';
diag_data_buf_snk_in_arr(i).err <= (OTHERS=>'0');
END GENERATE;
-----------------------------------------------------------------------------
-- Diagnostic Data Buffer (Records 1024 raw ADC samples after the PPS)
-- ToDo: Remove this JESD DB when the second (BSN) data buffer is working correctly
-----------------------------------------------------------------------------
u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_technology => g_technology,
g_nof_streams => c_nof_streams_db,
g_data_w => c_data_w,
g_buf_nof_data => 1024,
g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => rx_rst,
dp_clk => rx_clk,
ram_data_buf_mosi => ram_diag_data_buf_jesd_mosi,
ram_data_buf_miso => ram_diag_data_buf_jesd_miso,
reg_data_buf_mosi => reg_diag_data_buf_jesd_mosi,
reg_data_buf_miso => reg_diag_data_buf_jesd_miso,
in_sosi_arr => diag_data_buf_snk_in_arr,
in_sync => rx_sysref
);
-----------------------------------------------------------------------------
-- Time delay: dp_shiftram
-- . copied from unb1_bn_capture_input (apertif)
......@@ -262,7 +250,7 @@ BEGIN
dp_rst => rx_rst,
dp_clk => rx_clk,
mm_rst => mm_rst,
mm_rst => mm_rst_internal,
mm_clk => mm_clk,
sync_in => bs_sosi.sync,
......@@ -287,7 +275,7 @@ BEGIN
)
PORT MAP (
-- Clocks and reset
mm_rst => mm_rst,
mm_rst => mm_rst_internal,
mm_clk => mm_clk,
dp_rst => rx_rst,
dp_clk => rx_clk,
......@@ -308,7 +296,7 @@ BEGIN
)
PORT MAP (
-- Memory-mapped clock domain
mm_rst => mm_rst,
mm_rst => mm_rst_internal,
mm_clk => mm_clk,
reg_mosi => reg_bsn_scheduler_wg_mosi,
......@@ -345,7 +333,7 @@ BEGIN
)
PORT MAP (
-- Memory-mapped clock domain
mm_rst => mm_rst,
mm_rst => mm_rst_internal,
mm_clk => mm_clk,
reg_mosi => reg_wg_mosi,
......@@ -414,7 +402,7 @@ BEGIN
)
PORT MAP (
-- Memory-mapped clock domain
mm_rst => mm_rst,
mm_rst => mm_rst_internal,
mm_clk => mm_clk,
reg_mosi => reg_bsn_monitor_input_mosi,
reg_miso => reg_bsn_monitor_input_miso,
......@@ -441,7 +429,7 @@ BEGIN
)
PORT MAP (
-- Memory-mapped clock domain
mm_rst => mm_rst,
mm_rst => mm_rst_internal,
mm_clk => mm_clk,
reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
......@@ -470,7 +458,7 @@ BEGIN
g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
)
PORT MAP (
mm_rst => mm_rst,
mm_rst => mm_rst_internal,
mm_clk => mm_clk,
dp_rst => rx_rst,
dp_clk => rx_clk,
......@@ -510,4 +498,28 @@ BEGIN
);
END GENERATE;
-----------------------------------------------------------------------------
-- JESD Control register
-----------------------------------------------------------------------------
u_mm_jesd_ctrl_reg : ENTITY common_lib.common_reg_r_w
GENERIC MAP (
g_reg => c_mm_jesd_ctrl_reg,
g_init_reg => (OTHERS => '0')
)
PORT MAP (
rst => mm_rst,
clk => mm_clk,
-- control side
wr_en => jesd_ctrl_mosi.wr,
wr_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
wr_dat => jesd_ctrl_mosi.wrdata(c_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
rd_en => jesd_ctrl_mosi.rd,
rd_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
rd_dat => jesd_ctrl_miso.rddata(c_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
rd_val => OPEN,
-- data side
out_reg => mm_jesd_ctrl_reg,
in_reg => mm_jesd_ctrl_reg
);
END str;
applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+ 8
− 15
View file @ 34eaf737
......@@ -200,20 +200,6 @@ PACKAGE qsys_lofar2_unb2b_adc_pkg IS
rom_system_info_reset_export : out std_logic; -- export
rom_system_info_write_export : out std_logic; -- export
rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_data_buf_jesd_address_export : out std_logic_vector(15 downto 0); -- export
ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
ram_diag_data_buf_jesd_read_export : out std_logic; -- export
ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
ram_diag_data_buf_jesd_write_export : out std_logic; -- export
ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_data_buf_jesd_address_export : out std_logic_vector(11 downto 0); -- export
reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
reg_diag_data_buf_jesd_read_export : out std_logic; -- export
reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
reg_diag_data_buf_jesd_write_export : out std_logic; -- export
reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_aduh_monitor_address_export : out std_logic_vector(11 downto 0); -- export
ram_aduh_monitor_clk_export : out std_logic; -- export
ram_aduh_monitor_read_export : out std_logic; -- export
......@@ -241,7 +227,14 @@ PACKAGE qsys_lofar2_unb2b_adc_pkg IS
reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
reg_diag_data_buf_bsn_write_export : out std_logic; -- export
reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0) -- export
reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
pio_jesd_ctrl_reset_export : out std_logic; -- export
pio_jesd_ctrl_clk_export : out std_logic; -- export
pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
pio_jesd_ctrl_write_export : out std_logic; -- export
pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
pio_jesd_ctrl_read_export : out std_logic; -- export
pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
);
end component qsys_lofar2_unb2b_adc;
......
libraries/technology/ip_arria10_e1sg/generate-all-ip.sh 0 → 100755
+ 21
− 0
View file @ 34eaf737
#!/bin/bash
files=`find $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg -name 'generate_ip.sh' `
echo -e "About to generate the following IP blocks:\n$files\n"
for f in $files ; do
cd `dirname $f`
echo
echo -n "Entering directory: "
pwd
echo
rm -rf generated
./`basename $f`
cd -
done
echo "Done"
libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
+ 4
− 4
View file @ 34eaf737
......@@ -18,16 +18,16 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
$RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx/ip_arria10_e1sg_jesd204b_rx.qip
$RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.qip
$RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/ip_arria10_e1sg_jesd204b_rx_200MHz.qip
$RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.qip
$RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/ip_arria10_e1sg_jesd204b_rx_reset_seq.qip
$RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.qip
$RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_tx/ip_arria10_e1sg_jesd204b_tx.qip
[generate_ip_libs]
qsys-generate_ip_files =
ip_arria10_e1sg_jesd204b_rx.ip
ip_arria10_e1sg_jesd204b_rx_core_pll.ip
ip_arria10_e1sg_jesd204b_rx_200MHz.ip
ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.ip
ip_arria10_e1sg_jesd204b_rx_reset_seq.ip
ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.ip
ip_arria10_e1sg_jesd204b_tx.ip
......
libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+ 95
− 73
View file @ 34eaf737
......@@ -20,7 +20,7 @@
--
--------------------------------------------------------------------------------
-- Authors : J Hargreaves, L Hiemstra
-- Purpose: Combine IP components needed to create a JESD204B interface
-- Initially supports RX_ONLY for receiving data from an ADC
-- Description
......@@ -28,7 +28,6 @@
-- The sync_n signals are gated together to form g_nof_sync_n outputs
--
--LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e1sg_jesd204b_rx, ip_arria10_e1sg_jesd204b_rx_reset_seq, ip_arria10_e1sg_jesd204b_rx_core_pll, ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12;
LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e1sg_jesd204b_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE technology_lib.technology_pkg.ALL;
......@@ -42,7 +41,8 @@ ENTITY ip_arria10_e1sg_jesd204b IS
g_sim : BOOLEAN := FALSE;
g_nof_streams : NATURAL := 1;
g_nof_sync_n : NATURAL := 1;
g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY"
g_direction : STRING := "RX_ONLY"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
g_jesd_freq : STRING := "200MHz"
);
PORT (
-- JESD204B external signals
......@@ -59,6 +59,7 @@ ENTITY ip_arria10_e1sg_jesd204b IS
-- MM Control
mm_clk : IN STD_LOGIC;
mm_rst : IN STD_LOGIC;
jesd204b_disable_arr : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
jesd204b_mosi : IN t_mem_mosi; -- mm control
jesd204b_miso : OUT t_mem_miso;
......@@ -116,6 +117,8 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL jesd204b_sysref_2 : STD_LOGIC;
SIGNAL jesd204b_sysref_frameclk_1 : STD_LOGIC;
SIGNAL jesd204b_sysref_frameclk_2 : STD_LOGIC;
SIGNAL jesd204b_sysref_linkclk_1 : STD_LOGIC;
SIGNAL jesd204b_sysref_linkclk_2 : STD_LOGIC;
-- Data path
SIGNAL jesd204b_rx_link_data_arr : STD_LOGIC_VECTOR(c_jesd204b_rx_data_w*g_nof_streams-1 DOWNTO 0);
......@@ -123,13 +126,14 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL jesd204b_rx_somf_arr : STD_LOGIC_VECTOR(c_jesd204b_rx_somf_w*g_nof_streams-1 DOWNTO 0);
SIGNAL jesd204b_sync_n_internal_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
SIGNAL jesd204b_sync_n_enabled_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Component declarations for the IP blocks
component ip_arria10_e1sg_jesd204b_rx is
component ip_arria10_e1sg_jesd204b_rx_200MHz is
port (
alldev_lane_aligned : in std_logic := 'X'; -- export
csr_cf : out std_logic_vector(4 downto 0); -- export
......@@ -178,9 +182,9 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
somf : out std_logic_vector(c_jesd204b_rx_somf_w-1 downto 0); -- export
sysref : in std_logic := 'X' -- export
);
end component ip_arria10_e1sg_jesd204b_rx;
end component ip_arria10_e1sg_jesd204b_rx_200MHz;
component ip_arria10_e1sg_jesd204b_rx_core_pll is
component ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz is
port (
locked : out std_logic; -- export
outclk_0 : out std_logic; -- clk
......@@ -188,7 +192,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X' -- reset
);
end component ip_arria10_e1sg_jesd204b_rx_core_pll;
end component ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz;
component ip_arria10_e1sg_jesd204b_rx_reset_seq is
port (
......@@ -230,7 +234,8 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
BEGIN
-- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
-- Therefore a reset of mm_rst effectively resets the entire ip_arria10_e1sg_jesd204b and causes a reset on the rx_rst output.
rx_clk <= rxframe_clk;
rx_rst <= not core_pll_locked;
......@@ -253,7 +258,8 @@ BEGIN
-- The JESD204 IP (rx only)
-----------------------------------------------------------------------------
u_ip_arria10_e1sg_jesd204b_rx : ip_arria10_e1sg_jesd204b_rx
gen_jesd204b_rx_freqsel : IF g_jesd_freq = "200MHz" GENERATE
u_ip_arria10_e1sg_jesd204b_rx_200MHz : ip_arria10_e1sg_jesd204b_rx_200MHz
PORT MAP
(
alldev_lane_aligned => dev_lane_aligned_arr(i),
......@@ -271,15 +277,15 @@ BEGIN
csr_s => OPEN,
dev_lane_aligned => dev_lane_aligned_arr(i),
dev_sync_n => jesd204b_sync_n_internal_arr(i),
jesd204_rx_avs_chipselect => '1', --jesd204b_mosi_arr(i).chipselect,
jesd204_rx_avs_chipselect => '1',
jesd204_rx_avs_address => jesd204b_mosi_arr(i).address(c_jesd204b_mm_addr_w-1 downto 0),
jesd204_rx_avs_read => jesd204b_mosi_arr(i).rd,
jesd204_rx_avs_readdata => jesd204b_miso_arr(i).rddata(31 downto 0),
jesd204_rx_avs_waitrequest => jesd204b_miso_arr(i).waitrequest,
jesd204_rx_avs_write => jesd204b_mosi_arr(i).wr,
jesd204_rx_avs_writedata => jesd204b_mosi_arr(i).wrdata(31 downto 0),
jesd204_rx_avs_clk => jesd204b_avs_clk, --mm_clk,
jesd204_rx_avs_rst_n => rx_avs_rst_n_arr(i), -- Todo: Check if this could use mm_rst,
jesd204_rx_avs_clk => jesd204b_avs_clk,
jesd204_rx_avs_rst_n => rx_avs_rst_n_arr(i),
jesd204_rx_dlb_data => (others => '0'), -- debug/loopback testing
jesd204_rx_dlb_data_valid => (others => '0'), -- debug/loopback testing
jesd204_rx_dlb_disperr => (others => '0'), -- debug/loopback testing
......@@ -296,20 +302,21 @@ BEGIN
rx_digitalreset => rx_digitalreset_arr(I DOWNTO I),
rx_islockedtodata => rx_islockedtodata_arr(I DOWNTO I),
rx_serial_data => serial_rx_arr(i downto i),
rxlink_clk => rxlink_clk, -- TODO: still not clear if this should be 100MHz or 200MHz (Intel JESD204B-UG p63)
rxlink_clk => rxlink_clk,
rxlink_rst_n_reset_n => rxlink_rst_n_arr(i), -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
rxphy_clk => OPEN, -- Not used in Subclass 0 (Intel JESD204B-UG p63)
sof => OPEN,
somf => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_somf_w-1 downto c_jesd204b_rx_somf_w*i),
sysref => jesd204b_sysref_2
);
END GENERATE;
-----------------------------------------------------------------------------
-- Reset sequencer for each channel
-----------------------------------------------------------------------------
u_ip_arria10_e1sg_jesd204b_rx_reset_seq : ip_arria10_e1sg_jesd204b_rx_reset_seq
PORT MAP (
av_address => reset_seq_mosi_arr(i).address(7 downto 0), -- in std_logic_vector(7 downto 0) := (others => '0');
av_address => reset_seq_mosi_arr(i).address(7 downto 0),
av_readdata => reset_seq_miso_arr(i).rddata(31 downto 0),
av_read => reset_seq_mosi_arr(i).rd,
av_writedata => reset_seq_mosi_arr(i).wrdata(31 downto 0),
......@@ -322,7 +329,7 @@ BEGIN
reset5_dsrt_qual => rx_xcvr_ready_in_arr(i),
reset_in0 => mm_rst,
reset_out0 => pll_reset_arr(i), -- Use channel 0 to reset the core pll
reset_out1 => xcvr_rst_arr(i), -- Use channel 0 to reset the transceiver reset controller
reset_out1 => xcvr_rst_arr(i), -- Use channel 1 to reset the transceiver reset controller
reset_out2 => open,
reset_out3 => open,
reset_out4 => open,
......@@ -331,7 +338,6 @@ BEGIN
reset_out7 => rxframe_rst_arr(i)
);
--rx_xcvr_ready_in_arr(i) <= rx_csr_lane_powerdown_arr(i) OR xcvr_rst_ctrl_rx_ready_arr(i);
rx_xcvr_ready_in_arr(i) <= '1' when rx_csr_lane_powerdown_arr(i)='1' OR xcvr_rst_ctrl_rx_ready_arr(i)='1' else '0';
-- Invert thr active-low resets
......@@ -351,6 +357,7 @@ BEGIN
rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w-1 downto 0) <= (OTHERS => '0');
rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w-1 downto 0) <= (OTHERS => '0');
f2_div1_cnt_arr(i) <= '0';
rx_src_out_arr(i).valid <= '0';
ELSE
rx_src_out_arr(i).valid <= jesd204b_rx_link_valid_arr(i);
IF jesd204b_rx_link_valid_arr(i) = '0' THEN
......@@ -374,6 +381,8 @@ BEGIN
-----------------------------------------------------------------------------
-- Reclock sysref and the sync_n output
-- See: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf
-- Figure 25, page 151
-----------------------------------------------------------------------------
p_reclocksysref : PROCESS (rxlink_clk, core_pll_locked)
BEGIN
......@@ -390,8 +399,9 @@ BEGIN
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Capture sysref on the frame clock for export
-- Move sysref from rxlink_clk to rxframe_clk
-----------------------------------------------------------------------------
p_rx_sysref : PROCESS (rxframe_clk, core_pll_locked)
BEGIN
......@@ -401,8 +411,8 @@ BEGIN
rx_sysref <= '0';
ELSE
IF rising_edge(rxframe_clk) THEN
jesd204b_sysref_frameclk_1 <= jesd204b_sysref;
jesd204b_sysref_frameclk_2 <= jesd204b_sysref_frameclk_1;
jesd204b_sysref_frameclk_1 <= jesd204b_sysref_2; -- sysref from rxlink_clk domain
jesd204b_sysref_frameclk_2 <= jesd204b_sysref_linkclk_1;
IF jesd204b_sysref_frameclk_1 = '1' and jesd204b_sysref_frameclk_2 = '0' THEN
rx_sysref <= '1';
ELSE
......@@ -414,14 +424,16 @@ BEGIN
-- IOPLL in source synchronous or normal mode. (Intel JESD204B-UG p66)
u_ip_arria10_e1sg_jesd204b_rx_corepll : ip_arria10_e1sg_jesd204b_rx_core_pll
gen_jesd204b_rx_corepll_freqsel : IF g_jesd_freq = "200MHz" GENERATE
u_ip_arria10_e1sg_jesd204b_rx_corepll_200MHz : ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz
PORT MAP (
locked => core_pll_locked,
outclk_0 => rxlink_clk,
outclk_1 => rxframe_clk,
refclk => jesd204b_refclk,
outclk_0 => rxlink_clk, -- out 100 MHz
outclk_1 => rxframe_clk, -- out 200 MHz
refclk => jesd204b_refclk, -- in 200 MHz
rst => pll_reset_arr(0)
);
END GENERATE;
p_pll_locked_reg : PROCESS (mm_rst, mm_clk)
BEGIN
......@@ -451,12 +463,22 @@ BEGIN
END GENERATE;
gen_enable_sync_n : FOR i IN 0 TO g_nof_streams-1 GENERATE
-- The sync_n_enabled output is active '0'. For disabled signal inputs the sync_n_enabled output is forced to '1', so that for the disabled (= inactive = not used)
-- signal inputs the sync_n_internal from the JESD IP will not pull sync_n_enabled low.
-- The purpose of being able to disable inactive signal inputs is that this avoids that one inactive signal input will cause all signal inputs in a group that share
-- the sync_n_combined to become unavailable (see gen_group_sync_n).
-- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will not be used
jesd204b_sync_n_enabled_arr(i) <= jesd204b_sync_n_internal_arr(i) OR jesd204b_disable_arr(i);
END GENERATE;
-----------------------------------------------------------------------------
-- Group the SYNC_N outputs
-----------------------------------------------------------------------------
gen_group_sync_n : FOR i IN 0 TO g_nof_sync_n-1 GENERATE
jesd204b_sync_n_combined_arr(i) <= vector_and(jesd204b_sync_n_internal_arr(c_nof_sync_n_per_group*i+c_nof_sync_n_per_group-1 downto c_nof_sync_n_per_group*i));
jesd204b_sync_n_combined_arr(i) <= vector_and(jesd204b_sync_n_enabled_arr(c_nof_sync_n_per_group*i+c_nof_sync_n_per_group-1 downto c_nof_sync_n_per_group*i));
END GENERATE;
-----------------------------------------------------------------------------
......
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