Skip to content
Snippets Groups Projects
Commit 349c2643 authored by Reinier van der Walle's avatar Reinier van der Walle
Browse files

updated qsys design

parent 93425233
No related branches found
No related tags found
2 merge requests!277Resolve DIST2-2,!276Resolve DISTURB-2
Pipeline #34410 passed
Stage: simulation
Stage: synthesis
Expand all Hide whitespace changes
Inline Side-by-side
Showing
with 128 additions and 116 deletions
applications/disturb2/designs/disturb2_unb2b_station/quartus/ip/qsys_disturb2_unb2b_station/qsys_disturb2_unb2b_station_cpu_0.ip
+ 2
− 2
View file @ 349c2643
......@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xE0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xE0000' end='0x100000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x100000' end='0x110000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x110000' end='0x120000' datawidth='32' /><slave name='ram_wg.mem' start='0x120000' end='0x130000' datawidth='32' /><slave name='jesd204b.mem' start='0x130000' end='0x134000' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x134000' end='0x134400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x134400' end='0x134600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x134600' end='0x134800' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x134800' end='0x134A00' datawidth='32' /><slave name='reg_wg.mem' start='0x134A00' end='0x134B00' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x134B00' end='0x134C00' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x134C00' end='0x134D00' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x134D00' end='0x134E00' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x134E00' end='0x134E80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x134E80' end='0x134F00' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x134F00' end='0x134F80' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x134F80' end='0x134FC0' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x134FC0' end='0x135000' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x135000' end='0x135040' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x135040' end='0x135080' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x135080' end='0x1350C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x1350C0' end='0x135100' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x135100' end='0x135140' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x135140' end='0x135180' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x135180' end='0x1351A0' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x1351A0' end='0x1351C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x1351C0' end='0x1351E0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x1351E0' end='0x135200' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x135200' end='0x135220' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x135220' end='0x135240' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x135240' end='0x135260' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x135260' end='0x135280' datawidth='32' /><slave name='reg_epcs.mem' start='0x135280' end='0x1352A0' datawidth='32' /><slave name='reg_remu.mem' start='0x1352A0' end='0x1352C0' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x1352C0' end='0x1352D0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x1352D0' end='0x1352E0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x1352E0' end='0x1352F0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x1352F0' end='0x135300' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x135300' end='0x135310' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x135310' end='0x135320' datawidth='32' /><slave name='pio_pps.mem' start='0x135320' end='0x135330' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x135330' end='0x135338' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x135338' end='0x135340' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x135340' end='0x135348' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x135348' end='0x135350' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x135350' end='0x135358' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x135358' end='0x135360' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x135360' end='0x135368' datawidth='32' /><slave name='reg_si.mem' start='0x135368' end='0x135370' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x135370' end='0x135378' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x135378' end='0x135380' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x135380' end='0x135388' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x135388' end='0x135390' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x135390' end='0x135398' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
<spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xE0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xE0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x110000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x110000' end='0x120000' datawidth='32' /><slave name='ram_wg.mem' start='0x120000' end='0x130000' datawidth='32' /><slave name='jesd204b.mem' start='0x130000' end='0x134000' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x134000' end='0x134400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x134400' end='0x134600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x134600' end='0x134800' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x134800' end='0x134A00' datawidth='32' /><slave name='reg_wg.mem' start='0x134A00' end='0x134B00' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x134B00' end='0x134C00' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x134C00' end='0x134D00' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x134D00' end='0x134E00' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x134E00' end='0x134E80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x134E80' end='0x134F00' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x134F00' end='0x134F80' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x134F80' end='0x134FC0' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x134FC0' end='0x135000' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x135000' end='0x135040' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x135040' end='0x135080' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x135080' end='0x1350C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x1350C0' end='0x135100' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x135100' end='0x135140' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x135140' end='0x135180' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x135180' end='0x1351A0' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x1351A0' end='0x1351C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x1351C0' end='0x1351E0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x1351E0' end='0x135200' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x135200' end='0x135220' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x135220' end='0x135240' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x135240' end='0x135260' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x135260' end='0x135280' datawidth='32' /><slave name='reg_epcs.mem' start='0x135280' end='0x1352A0' datawidth='32' /><slave name='reg_remu.mem' start='0x1352A0' end='0x1352C0' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x1352C0' end='0x1352D0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x1352D0' end='0x1352E0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x1352E0' end='0x1352F0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x1352F0' end='0x135300' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x135300' end='0x135310' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x135310' end='0x135320' datawidth='32' /><slave name='pio_pps.mem' start='0x135320' end='0x135330' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x135330' end='0x135338' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x135338' end='0x135340' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x135340' end='0x135348' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x135348' end='0x135350' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x135350' end='0x135358' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x135358' end='0x135360' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x135360' end='0x135368' datawidth='32' /><slave name='reg_si.mem' start='0x135368' end='0x135370' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x135370' end='0x135378' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x135378' end='0x135380' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x135380' end='0x135388' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x135388' end='0x135390' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x135390' end='0x135398' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
......@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xC0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xE0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0x100000' end='0x110000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x110000' end='0x120000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0x120000' end='0x130000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x130000' end='0x134000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x134000' end='0x134400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x134400' end='0x134600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x134600' end='0x134800' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x134800' end='0x134A00' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x134A00' end='0x134B00' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x134B00' end='0x134C00' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x134C00' end='0x134D00' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x134D00' end='0x134E00' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_xsub.mem' start='0x134E00' end='0x134E80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x134E80' end='0x134F00' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x134F00' end='0x134F80' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x134F80' end='0x134FC0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x134FC0' end='0x135000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x135000' end='0x135040' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x135040' end='0x135080' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x135080' end='0x1350C0' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x1350C0' end='0x135100' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x135100' end='0x135140' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x135140' end='0x135180' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x135180' end='0x1351A0' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_bf.mem' start='0x1351A0' end='0x1351C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x1351C0' end='0x1351E0' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x1351E0' end='0x135200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x135200' end='0x135220' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x135220' end='0x135240' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x135240' end='0x135260' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x135260' end='0x135280' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x135280' end='0x1352A0' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x1352A0' end='0x1352C0' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_bf.mem' start='0x1352C0' end='0x1352D0' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x1352D0' end='0x1352E0' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x1352E0' end='0x1352F0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x1352F0' end='0x135300' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x135300' end='0x135310' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x135310' end='0x135320' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x135320' end='0x135330' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x135330' end='0x135338' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x135338' end='0x135340' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x135340' end='0x135348' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x135348' end='0x135350' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x135350' end='0x135358' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x135358' end='0x135360' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x135360' end='0x135368' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x135368' end='0x135370' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x135370' end='0x135378' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x135378' end='0x135380' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x135380' end='0x135388' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x135388' end='0x135390' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x135390' end='0x135398' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
<value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xC0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xE0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x100000' end='0x110000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0x110000' end='0x120000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0x120000' end='0x130000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x130000' end='0x134000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x134000' end='0x134400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x134400' end='0x134600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x134600' end='0x134800' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x134800' end='0x134A00' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x134A00' end='0x134B00' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x134B00' end='0x134C00' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x134C00' end='0x134D00' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x134D00' end='0x134E00' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_xsub.mem' start='0x134E00' end='0x134E80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x134E80' end='0x134F00' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x134F00' end='0x134F80' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x134F80' end='0x134FC0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x134FC0' end='0x135000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x135000' end='0x135040' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x135040' end='0x135080' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x135080' end='0x1350C0' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x1350C0' end='0x135100' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x135100' end='0x135140' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x135140' end='0x135180' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x135180' end='0x1351A0' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_bf.mem' start='0x1351A0' end='0x1351C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x1351C0' end='0x1351E0' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x1351E0' end='0x135200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x135200' end='0x135220' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x135220' end='0x135240' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x135240' end='0x135260' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x135260' end='0x135280' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x135280' end='0x1352A0' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x1352A0' end='0x1352C0' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_bf.mem' start='0x1352C0' end='0x1352D0' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x1352D0' end='0x1352E0' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x1352E0' end='0x1352F0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x1352F0' end='0x135300' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x135300' end='0x135310' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x135310' end='0x135320' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x135320' end='0x135330' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x135330' end='0x135338' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x135338' end='0x135340' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x135340' end='0x135348' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x135348' end='0x135350' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x135350' end='0x135358' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x135358' end='0x135360' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x135360' end='0x135368' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x135368' end='0x135370' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x135370' end='0x135378' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x135378' end='0x135380' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x135380' end='0x135388' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x135388' end='0x135390' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x135390' end='0x135398' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
......
applications/disturb2/designs/disturb2_unb2b_station/quartus/ip/qsys_disturb2_unb2b_station/qsys_disturb2_unb2b_station_ram_bf_weights.ip
+ 7
− 4
View file @ 349c2643
......@@ -259,7 +259,7 @@
<spirit:parameter>
<spirit:name>readLatency</spirit:name>
<spirit:displayName>Read latency</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
<spirit:value spirit:format="long" spirit:id="readLatency">2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>readWaitStates</spirit:name>
......@@ -570,7 +570,7 @@
<spirit:view>
<spirit:name>QUARTUS_SYNTH</spirit:name>
<spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
<spirit:modelName>avs_common_mm</spirit:modelName>
<spirit:modelName>avs_common_mm_readlatency2</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>QUARTUS_SYNTH</spirit:localName>
</spirit:fileSetRef>
......@@ -775,7 +775,7 @@
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
<spirit:library>qsys_disturb2_unb2b_station_ram_bf_weights</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:name>avs_common_mm_readlatency2</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
<altera:altera_module_parameters>
......@@ -824,6 +824,9 @@
<spirit:displayName>bonusData</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="bonusData">bonusData
{
element qsys_disturb2_unb2b_station_bf_weights
{
}
}
</spirit:value>
</spirit:parameter>
......@@ -1082,7 +1085,7 @@
</entry>
<entry>
<key>readLatency</key>
<value>1</value>
<value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
......
applications/disturb2/designs/disturb2_unb2b_station/quartus/ip/qsys_disturb2_unb2b_station/qsys_disturb2_unb2b_station_ram_equalizer_gains.ip
+ 15
− 15
View file @ 349c2643
......@@ -2,7 +2,7 @@
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
<spirit:library>qsys_disturb2_unb2b_station_ram_equalizer_gains</spirit:library>
<spirit:name>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</spirit:name>
<spirit:name>qsys_disturb2_unb2b_station_ram_equalizer_gains</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
......@@ -259,7 +259,7 @@
<spirit:parameter>
<spirit:name>readLatency</spirit:name>
<spirit:displayName>Read latency</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
<spirit:value spirit:format="long" spirit:id="readLatency">2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>readWaitStates</spirit:name>
......@@ -570,7 +570,7 @@
<spirit:view>
<spirit:name>QUARTUS_SYNTH</spirit:name>
<spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
<spirit:modelName>avs_common_mm</spirit:modelName>
<spirit:modelName>avs_common_mm_readlatency2</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>QUARTUS_SYNTH</spirit:localName>
</spirit:fileSetRef>
......@@ -775,7 +775,7 @@
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
<spirit:library>qsys_disturb2_unb2b_station_ram_equalizer_gains</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:name>avs_common_mm_readlatency2</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
<altera:altera_module_parameters>
......@@ -1082,7 +1082,7 @@
</entry>
<entry>
<key>readLatency</key>
<value>1</value>
<value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
......@@ -1406,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
<altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.address" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="address" altera:internal="qsys_disturb2_unb2b_station_ram_equalizer_gains.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.clk" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="clk" altera:internal="qsys_disturb2_unb2b_station_ram_equalizer_gains.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.mem" altera:type="avalon" altera:dir="end">
<altera:interface_mapping altera:name="mem" altera:internal="qsys_disturb2_unb2b_station_ram_equalizer_gains.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.read" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="read" altera:internal="qsys_disturb2_unb2b_station_ram_equalizer_gains.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.readdata" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="readdata" altera:internal="qsys_disturb2_unb2b_station_ram_equalizer_gains.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.reset" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="reset" altera:internal="qsys_disturb2_unb2b_station_ram_equalizer_gains.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.system" altera:type="clock" altera:dir="end">
<altera:interface_mapping altera:name="system" altera:internal="qsys_disturb2_unb2b_station_ram_equalizer_gains.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.system_reset" altera:type="reset" altera:dir="end">
<altera:interface_mapping altera:name="system_reset" altera:internal="qsys_disturb2_unb2b_station_ram_equalizer_gains.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.write" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="write" altera:internal="qsys_disturb2_unb2b_station_ram_equalizer_gains.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.writedata" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="writedata" altera:internal="qsys_disturb2_unb2b_station_ram_equalizer_gains.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
......
applications/disturb2/designs/disturb2_unb2b_station/src/vhdl/qsys_disturb2_unb2b_station_pkg.vhd
+ 2
− 1
View file @ 349c2643
-------------------------------------------------------------------------------
--
-- Copyright 2020
-- Copyright 2022
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
......@@ -570,5 +570,6 @@ PACKAGE qsys_disturb2_unb2b_station_pkg IS
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_disturb2_unb2b_station;
END qsys_disturb2_unb2b_station_pkg;
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment