Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
H
HDL
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Container registry
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
GitLab community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
RTSD
HDL
Commits
342f7496
Commit
342f7496
authored
9 years ago
by
Zanting
Browse files
Options
Downloads
Patches
Plain Diff
Moved pipelining to tech_mult_lib
parent
49fae287
No related branches found
No related tags found
No related merge requests found
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
+6
-31
6 additions, 31 deletions
libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
with
6 additions
and
31 deletions
libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
+
6
−
31
View file @
342f7496
...
@@ -84,21 +84,6 @@ ARCHITECTURE str OF common_complex_mult IS
...
@@ -84,21 +84,6 @@ ARCHITECTURE str OF common_complex_mult IS
-- Extra output pipelining is only needed when c_pipeline > c_dsp_latency
-- Extra output pipelining is only needed when c_pipeline > c_dsp_latency
CONSTANT
c_pipeline_output
:
NATURAL
:
=
sel_a_b
(
c_pipeline
>
c_dsp_latency
,
c_pipeline
-
c_dsp_latency
,
0
);
CONSTANT
c_pipeline_output
:
NATURAL
:
=
sel_a_b
(
c_pipeline
>
c_dsp_latency
,
c_pipeline
-
c_dsp_latency
,
0
);
-- Force to maximum 18 bit width, because:
-- . the ip_stratixiv_complex_mult is generated for 18b inputs and 36b output and then uses 4 real multipliers and no additional registers
-- . if one input > 18b then another IP needs to be regenerated and that will use 8 real multipliers and some extra LUTs and registers
-- . if both inputs > 18b then another IP needs to be regenerated and that will use 16 real multipliers and some extra LUTs and registers
-- . if the output is set to 18b+18b + 1b =37b to account for the sum then another IP needs to be regenerated and that will use some extra registers
-- ==> for inputs <= 18b this ip_stratixiv_complex_mult is appropriate and it can not be made parametrisable to fit also inputs > 18b.
CONSTANT
c_dsp_dat_w
:
NATURAL
:
=
18
;
CONSTANT
c_dsp_prod_w
:
NATURAL
:
=
2
*
c_dsp_dat_w
;
SIGNAL
ar
:
STD_LOGIC_VECTOR
(
c_dsp_dat_w
-1
DOWNTO
0
);
SIGNAL
ai
:
STD_LOGIC_VECTOR
(
c_dsp_dat_w
-1
DOWNTO
0
);
SIGNAL
br
:
STD_LOGIC_VECTOR
(
c_dsp_dat_w
-1
DOWNTO
0
);
SIGNAL
bi
:
STD_LOGIC_VECTOR
(
c_dsp_dat_w
-1
DOWNTO
0
);
SIGNAL
mult_re
:
STD_LOGIC_VECTOR
(
c_dsp_prod_w
-1
DOWNTO
0
);
SIGNAL
mult_im
:
STD_LOGIC_VECTOR
(
c_dsp_prod_w
-1
DOWNTO
0
);
SIGNAL
result_re
:
STD_LOGIC_VECTOR
(
g_out_p_w
-1
DOWNTO
0
);
SIGNAL
result_re
:
STD_LOGIC_VECTOR
(
g_out_p_w
-1
DOWNTO
0
);
SIGNAL
result_im
:
STD_LOGIC_VECTOR
(
g_out_p_w
-1
DOWNTO
0
);
SIGNAL
result_im
:
STD_LOGIC_VECTOR
(
g_out_p_w
-1
DOWNTO
0
);
...
@@ -122,12 +107,6 @@ BEGIN
...
@@ -122,12 +107,6 @@ BEGIN
out_dat
=>
out_val
out_dat
=>
out_val
);
);
-- Adapt DSP input widths
ar
<=
RESIZE_SVEC
(
in_ar
,
c_dsp_dat_w
);
ai
<=
RESIZE_SVEC
(
in_ai
,
c_dsp_dat_w
);
br
<=
RESIZE_SVEC
(
in_br
,
c_dsp_dat_w
);
bi
<=
RESIZE_SVEC
(
in_bi
,
c_dsp_dat_w
)
WHEN
g_conjugate_b
=
FALSE
ELSE
TO_SVEC
(
-
TO_SINT
(
in_bi
),
c_dsp_dat_w
);
u_complex_mult
:
ENTITY
tech_mult_lib
.
tech_complex_mult
u_complex_mult
:
ENTITY
tech_mult_lib
.
tech_complex_mult
GENERIC
MAP
(
GENERIC
MAP
(
g_technology
=>
g_technology
,
g_technology
=>
g_technology
,
...
@@ -145,18 +124,14 @@ u_complex_mult : ENTITY tech_mult_lib.tech_complex_mult
...
@@ -145,18 +124,14 @@ u_complex_mult : ENTITY tech_mult_lib.tech_complex_mult
rst
=>
rst
,
rst
=>
rst
,
clk
=>
clk
,
clk
=>
clk
,
clken
=>
clken
,
clken
=>
clken
,
in_ar
=>
ar
,
in_ar
=>
in_
ar
,
in_ai
=>
ai
,
in_ai
=>
in_
ai
,
in_br
=>
br
,
in_br
=>
in_
br
,
in_bi
=>
bi
,
in_bi
=>
in_
bi
,
out_pr
=>
m
ult_re
,
result_re
=>
res
ult_re
,
out_pi
=>
m
ult_im
result_im
=>
res
ult_im
);
);
-- Back to true input widths and then resize for output width
result_re
<=
RESIZE_SVEC
(
mult_re
,
g_out_p_w
);
result_im
<=
RESIZE_SVEC
(
mult_im
,
g_out_p_w
);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Extra output pipelining
-- Extra output pipelining
------------------------------------------------------------------------------
------------------------------------------------------------------------------
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment