diff --git a/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd b/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
index 38e6024671330d65d44d73e2eb9ab68b149491f9..4844faf0e1558d81984343bcee4bacd853cc02aa 100644
--- a/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
@@ -84,21 +84,6 @@ ARCHITECTURE str OF common_complex_mult IS
   -- Extra output pipelining is only needed when c_pipeline > c_dsp_latency
   CONSTANT c_pipeline_output : NATURAL := sel_a_b(c_pipeline>c_dsp_latency, c_pipeline-c_dsp_latency, 0);  
   
-  -- Force to maximum 18 bit width, because:
-  -- . the ip_stratixiv_complex_mult is generated for 18b inputs and 36b output and then uses 4 real multipliers and no additional registers
-  -- . if one input   > 18b then another IP needs to be regenerated and that will use  8 real multipliers and some extra LUTs and registers
-  -- . if both inputs > 18b then another IP needs to be regenerated and that will use 16 real multipliers and some extra LUTs and registers
-  -- . if the output is set to 18b+18b + 1b =37b to account for the sum then another IP needs to be regenerated and that will use some extra registers
-  -- ==> for inputs <= 18b this ip_stratixiv_complex_mult is appropriate and it can not be made parametrisable to fit also inputs > 18b.
-  CONSTANT c_dsp_dat_w    : NATURAL  := 18;
-  CONSTANT c_dsp_prod_w   : NATURAL  := 2*c_dsp_dat_w;
-  
-  SIGNAL ar        : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
-  SIGNAL ai        : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
-  SIGNAL br        : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
-  SIGNAL bi        : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
-  SIGNAL mult_re   : STD_LOGIC_VECTOR(c_dsp_prod_w-1 DOWNTO 0);
-  SIGNAL mult_im   : STD_LOGIC_VECTOR(c_dsp_prod_w-1 DOWNTO 0);
   SIGNAL result_re : STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
   SIGNAL result_im : STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
 
@@ -122,12 +107,6 @@ BEGIN
     out_dat => out_val
   );
 
-  -- Adapt DSP input widths
-  ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
-  ai <= RESIZE_SVEC(in_ai, c_dsp_dat_w);
-  br <= RESIZE_SVEC(in_br, c_dsp_dat_w);
-  bi <= RESIZE_SVEC(in_bi, c_dsp_dat_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_dat_w);
-
 u_complex_mult : ENTITY tech_mult_lib.tech_complex_mult
   GENERIC MAP(
     g_technology       => g_technology,
@@ -145,18 +124,14 @@ u_complex_mult : ENTITY tech_mult_lib.tech_complex_mult
     rst        => rst,
     clk        => clk,
     clken      => clken,
-    in_ar      => ar,
-    in_ai      => ai,
-    in_br      => br,
-    in_bi      => bi,
-    out_pr     => mult_re,
-    out_pi     => mult_im
+    in_ar      => in_ar,
+    in_ai      => in_ai,
+    in_br      => in_br,
+    in_bi      => in_bi,
+    result_re  => result_re,
+    result_im  => result_im
   );     
 
-  -- Back to true input widths and then resize for output width
-  result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
-  result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
-
   ------------------------------------------------------------------------------
   -- Extra output pipelining
   ------------------------------------------------------------------------------