From 340142155e0d0b66e6e143082bb0b8c561b0a3c6 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 6 Jan 2015 09:51:35 +0000
Subject: [PATCH] set MEM_TRCD=6 to avoid timing error message in simulation.
---
libraries/technology/ddr/tech_ddr_mem_model.vhd | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libraries/technology/ddr/tech_ddr_mem_model.vhd b/libraries/technology/ddr/tech_ddr_mem_model.vhd
index 9daf17cb9d..546849e8a8 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model.vhd
@@ -71,7 +71,7 @@ BEGIN
MEM_IF_DQ_WIDTH => g_tech_ddr.dq_w,
MEM_MIRROR_ADDRESSING_DEC => 0,
MEM_TRTP => 8,
- MEM_TRCD => 8,
+ MEM_TRCD => 6,
MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
MEM_REGDIMM_ENABLED => 0,
--
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