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Commit 33e83b5a authored by Eric Kooistra's avatar Eric Kooistra
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Added g_sim_model.

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libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd
+ 2
− 0
View file @ 33e83b5a
...@@ -56,6 +56,7 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL; ...@@ -56,6 +56,7 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY mms_io_ddr_diag IS ENTITY mms_io_ddr_diag IS
GENERIC ( GENERIC (
-- System -- System
g_sim_model_ddr : BOOLEAN := FALSE;
g_technology : NATURAL := c_tech_select_default; g_technology : NATURAL := c_tech_select_default;
g_dp_data_w : NATURAL := 32; -- DP data width, func_tech_ddr_ctlr_data_w(g_io_tech_ddr)/g_dp_data_w must be a power of 2 due to the mixed width FIFO g_dp_data_w : NATURAL := 32; -- DP data width, func_tech_ddr_ctlr_data_w(g_io_tech_ddr)/g_dp_data_w must be a power of 2 due to the mixed width FIFO
...@@ -156,6 +157,7 @@ BEGIN ...@@ -156,6 +157,7 @@ BEGIN
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
u_mms_io_ddr : ENTITY work.mms_io_ddr u_mms_io_ddr : ENTITY work.mms_io_ddr
GENERIC MAP ( GENERIC MAP (
g_sim_model => g_sim_model_ddr,
g_technology => g_technology, g_technology => g_technology,
g_tech_ddr => g_io_tech_ddr, g_tech_ddr => g_io_tech_ddr,
g_cross_domain_dvr_ctlr => TRUE, -- cross between mm_clk and ctlr_clk_in g_cross_domain_dvr_ctlr => TRUE, -- cross between mm_clk and ctlr_clk_in
......
libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+ 6
− 2
View file @ 33e83b5a
...@@ -44,6 +44,7 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL; ...@@ -44,6 +44,7 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY tb_io_ddr IS ENTITY tb_io_ddr IS
GENERIC ( GENERIC (
g_sim_model : BOOLEAN := FALSE;
g_technology : NATURAL := c_tech_select_default; g_technology : NATURAL := c_tech_select_default;
g_tech_ddr3 : t_c_tech_ddr := c_tech_ddr3_4g_800m_master; g_tech_ddr3 : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
g_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_4g_1600m; g_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
...@@ -69,8 +70,10 @@ END ENTITY tb_io_ddr; ...@@ -69,8 +70,10 @@ END ENTITY tb_io_ddr;
ARCHITECTURE str of tb_io_ddr IS ARCHITECTURE str of tb_io_ddr IS
-- Select DDR3 or DDR4 dependent on the technology -- Select DDR3 or DDR4 dependent on the technology and sim model
CONSTANT c_tech_ddr : t_c_tech_ddr := func_tech_sel_ddr(g_technology, g_tech_ddr3, g_tech_ddr4); CONSTANT c_mem_ddr : t_c_tech_ddr := func_tech_sel_ddr(g_technology, g_tech_ddr3, g_tech_ddr4);
CONSTANT c_sim_ddr : t_c_tech_ddr := func_tech_sel_ddr(g_technology, c_tech_ddr3_sim_16k, c_tech_ddr4_sim_16k);
CONSTANT c_tech_ddr : t_c_tech_ddr := func_tech_sel_ddr(g_sim_model, c_sim_ddr, c_mem_ddr);
CONSTANT c_cross_domain_dvr_ctlr : BOOLEAN := g_cross_domain_dvr_ctlr OR g_ctlr_ref_clk_period/=g_dvr_clk_period; CONSTANT c_cross_domain_dvr_ctlr : BOOLEAN := g_cross_domain_dvr_ctlr OR g_ctlr_ref_clk_period/=g_dvr_clk_period;
...@@ -401,6 +404,7 @@ BEGIN ...@@ -401,6 +404,7 @@ BEGIN
u_io_ddr: ENTITY work.io_ddr u_io_ddr: ENTITY work.io_ddr
GENERIC MAP( GENERIC MAP(
g_sim_model => g_sim_model,
g_technology => g_technology, g_technology => g_technology,
g_tech_ddr => c_tech_ddr, g_tech_ddr => c_tech_ddr,
g_cross_domain_dvr_ctlr => c_cross_domain_dvr_ctlr, g_cross_domain_dvr_ctlr => c_cross_domain_dvr_ctlr,
......
libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
+ 21
− 15
View file @ 33e83b5a
...@@ -38,6 +38,7 @@ END tb_tb_io_ddr; ...@@ -38,6 +38,7 @@ END tb_tb_io_ddr;
ARCHITECTURE tb OF tb_tb_io_ddr IS ARCHITECTURE tb OF tb_tb_io_ddr IS
CONSTANT c_sim_model : BOOLEAN := FALSE;
CONSTANT c_technology : NATURAL := c_tech_select_default; CONSTANT c_technology : NATURAL := c_tech_select_default;
CONSTANT c_tech_ddr3 : t_c_tech_ddr := c_tech_ddr3_4g_800m_master; CONSTANT c_tech_ddr3 : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
CONSTANT c_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_4g_1600m; CONSTANT c_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
...@@ -48,6 +49,7 @@ ARCHITECTURE tb OF tb_tb_io_ddr IS ...@@ -48,6 +49,7 @@ ARCHITECTURE tb OF tb_tb_io_ddr IS
BEGIN BEGIN
-- g_sim_model : BOOLEAN := FALSE;
-- g_technology : NATURAL := c_tech_select_default; -- g_technology : NATURAL := c_tech_select_default;
-- g_tech_ddr3 : t_c_tech_ddr := c_tech_ddr3_4g_800m_master; -- g_tech_ddr3 : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
-- g_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_4g_1600m; -- g_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
...@@ -66,29 +68,33 @@ BEGIN ...@@ -66,29 +68,33 @@ BEGIN
-- g_nof_repeat : NATURAL := 1; -- number of stimuli repeats with write flush after each repeat -- g_nof_repeat : NATURAL := 1; -- number of stimuli repeats with write flush after each repeat
-- g_wr_flush_mode : STRING := "SYN" -- "VAL", "SOP", "SYN" -- g_wr_flush_mode : STRING := "SYN" -- "VAL", "SOP", "SYN"
gen_ddr3 : IF c_tech_ddr.name="DDR3" GENERATE gen_sim_model: IF c_sim_model=TRUE GENERATE
u_default : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 512, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0)); u_sim_model : ENTITY work.tb_io_ddr GENERIC MAP ( TRUE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 512, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
END GENERATE;
gen_ddr3 : IF c_sim_model=FALSE AND c_tech_ddr.name="DDR3" GENERATE
u_default : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 512, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
u_fill_wrfifo_on_next_valid : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 1, 256, 1000, 2, 1, 4, 2, "VAL") PORT MAP (tb_end_vec(1)); u_fill_wrfifo_on_next_valid : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 1, 256, 1000, 2, 1, 4, 2, "VAL") PORT MAP (tb_end_vec(1));
u_fill_wrfifo_on_next_sop : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 1, 256, 1000, 2, 3, 4, 2, "SOP") PORT MAP (tb_end_vec(2)); u_fill_wrfifo_on_next_sop : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 1, 256, 1000, 2, 3, 4, 2, "SOP") PORT MAP (tb_end_vec(2));
u_fill_wrfifo_on_next_sync : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 1, 256, 1000, 2, 4, 1, 2, "SYN") PORT MAP (tb_end_vec(3)); u_fill_wrfifo_on_next_sync : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 1, 256, 1000, 2, 4, 1, 2, "SYN") PORT MAP (tb_end_vec(3));
u_cross_domain : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, TRUE, 5 ns, 5 ns, 5 ns, 8 ns, 1,8192, 2500, 1, 2, 3, 1, "VAL") PORT MAP (tb_end_vec(4)); u_cross_domain : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, TRUE, 5 ns, 5 ns, 5 ns, 8 ns, 1,8192, 2500, 1, 2, 3, 1, "VAL") PORT MAP (tb_end_vec(4));
u_mixed_width : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 8,8192, 2500, 1, 3, 2, 1, "VAL") PORT MAP (tb_end_vec(5)); u_mixed_width : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 8,8192, 2500, 1, 3, 2, 1, "VAL") PORT MAP (tb_end_vec(5));
u_wr_burst_size_0 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 2,10, 3, 3, 2, "VAL") PORT MAP (tb_end_vec(6)); u_wr_burst_size_0 : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 2,10, 3, 3, 2, "VAL") PORT MAP (tb_end_vec(6));
u_wr_burst_size_1 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 1,10, 1, 1, 2, "VAL") PORT MAP (tb_end_vec(7)); u_wr_burst_size_1 : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 1,10, 1, 1, 2, "VAL") PORT MAP (tb_end_vec(7));
u_cross_dvr_to_faster_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 20 ns, 5 ns, 8 ns, 1,8192, 2500, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(8)); u_cross_dvr_to_faster_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 20 ns, 5 ns, 8 ns, 1,8192, 2500, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(8));
u_cross_dvr_to_slower_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 1 ns, 5 ns, 8 ns, 1,8192, 2500, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(9)); u_cross_dvr_to_slower_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 1 ns, 5 ns, 8 ns, 1,8192, 2500, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(9));
u_sequencer_1_16 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 64,10, 1,16, 1, "VAL") PORT MAP (tb_end_vec(10)); u_sequencer_1_16 : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 64,10, 1,16, 1, "VAL") PORT MAP (tb_end_vec(10));
u_sequencer_16_1 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 64,10,16, 1, 1, "VAL") PORT MAP (tb_end_vec(11)); u_sequencer_16_1 : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 64,10,16, 1, 1, "VAL") PORT MAP (tb_end_vec(11));
END GENERATE; END GENERATE;
-- Distinghuis between tests for DDR3 and DDR4, because the Quartus 14.1 ip_arria10 DDR4 model simulates about 40x slower than the Quartus 11.1 ip_stratixiv DDR3 uniphy model. -- Distinghuis between tests for DDR3 and DDR4, because the Quartus 14.1 ip_arria10 DDR4 model simulates about 40x slower than the Quartus 11.1 ip_stratixiv DDR3 uniphy model.
gen_ddr4 : IF c_tech_ddr.name="DDR4" GENERATE gen_ddr4 : IF c_sim_model=FALSE AND c_tech_ddr.name="DDR4" GENERATE
u_default : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 512, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0)); u_default : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 512, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
END GENERATE; END GENERATE;
p_tb_end : PROCESS p_tb_end : PROCESS
......
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