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Commit 3375e335 authored by Eric Kooistra's avatar Eric Kooistra
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Merge branch 'synth_regression_fix' into 'master' 

added missing file paths

See merge request desp/hdl!346
parents eb24be54 2abcabfc
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1 merge request!346added missing file paths
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libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+ 4
− 0
View file @ 3375e335
......@@ -42,6 +42,8 @@ set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property quartus_synth ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd TOP_LEVEL_FILE
add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
add_fileset_file common_str_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_str_pkg.vhd
add_fileset_file common_field_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_field_pkg.vhd
add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
......@@ -52,6 +54,8 @@ set_fileset_property sim_vhdl ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property sim_vhdl ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd
add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
add_fileset_file common_str_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_str_pkg.vhd
add_fileset_file common_field_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_field_pkg.vhd
add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
......
libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
+ 2
− 0
View file @ 3375e335
......@@ -55,6 +55,8 @@ set_module_property FIX_110_VIP_PATH false
# | RadioHDL/trunk/libraries/io/eth/src/vhdl/
add_file avs2_eth_coe.vhd {SYNTHESIS SIMULATION}
add_file ../../../../base/common/src/vhdl/common_pkg.vhd {SYNTHESIS SIMULATION}
add_file ../../../../base/common/src/vhdl/common_str_pkg.vhd {SYNTHESIS SIMULATION}
add_file ../../../../base/common/src/vhdl/common_field_pkg.vhd {SYNTHESIS SIMULATION}
add_file ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd {SYNTHESIS SIMULATION}
add_file ../../../../technology/tse/tech_tse_pkg.vhd {SYNTHESIS SIMULATION}
add_file eth_pkg.vhd {SYNTHESIS SIMULATION}
......
libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
+ 2
− 0
View file @ 3375e335
......@@ -55,6 +55,8 @@ set_module_property FIX_110_VIP_PATH false
# | RadioHDL/trunk/libraries/io/eth/src/vhdl/
add_file avs2_eth_coe.vhd {SYNTHESIS SIMULATION}
add_file ../../../../base/common/src/vhdl/common_pkg.vhd {SYNTHESIS SIMULATION}
add_file ../../../../base/common/src/vhdl/common_str_pkg.vhd {SYNTHESIS SIMULATION}
add_file ../../../../base/common/src/vhdl/common_field_pkg.vhd {SYNTHESIS SIMULATION}
add_file ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd {SYNTHESIS SIMULATION}
add_file ../../../../technology/tse/tech_tse_pkg.vhd {SYNTHESIS SIMULATION}
add_file eth_pkg.vhd {SYNTHESIS SIMULATION}
......
libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
+ 2
− 0
View file @ 3375e335
......@@ -55,6 +55,8 @@ set_module_property FIX_110_VIP_PATH false
# | RadioHDL/trunk/libraries/io/eth/src/vhdl/
add_file avs2_eth_coe.vhd {SYNTHESIS SIMULATION}
add_file ../../../../base/common/src/vhdl/common_pkg.vhd {SYNTHESIS SIMULATION}
add_file ../../../../base/common/src/vhdl/common_str_pkg.vhd {SYNTHESIS SIMULATION}
add_file ../../../../base/common/src/vhdl/common_field_pkg.vhd {SYNTHESIS SIMULATION}
add_file ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd {SYNTHESIS SIMULATION}
add_file ../../../../technology/tse/tech_tse_pkg.vhd {SYNTHESIS SIMULATION}
add_file eth_pkg.vhd {SYNTHESIS SIMULATION}
......
libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl
+ 4
− 0
View file @ 3375e335
......@@ -42,6 +42,8 @@ set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property quartus_synth ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd TOP_LEVEL_FILE
add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
add_fileset_file common_str_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_str_pkg.vhd
add_fileset_file common_field_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_field_pkg.vhd
add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
......@@ -52,6 +54,8 @@ set_fileset_property sim_vhdl ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property sim_vhdl ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd
add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
add_fileset_file common_str_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_str_pkg.vhd
add_fileset_file common_field_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_field_pkg.vhd
add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
......
libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl
+ 4
− 0
View file @ 3375e335
......@@ -42,6 +42,8 @@ set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property quartus_synth ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd TOP_LEVEL_FILE
add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
add_fileset_file common_str_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_str_pkg.vhd
add_fileset_file common_field_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_field_pkg.vhd
add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
......@@ -52,6 +54,8 @@ set_fileset_property sim_vhdl ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property sim_vhdl ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd
add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
add_fileset_file common_str_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_str_pkg.vhd
add_fileset_file common_field_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_field_pkg.vhd
add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
......
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