decreased design_note field from 52B to 48B to fit the 32 word system

info

boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd

@@ -78,7 +78,7 @@ ARCHITECTURE rtl OF unb2b_board_system_info_reg IS
   CONSTANT c_nof_design_name_regs : NATURAL := 13; -- design_name
   CONSTANT c_nof_stamp_regs       : NATURAL := 2;  -- date, time
   CONSTANT c_nof_revision_id_regs : NATURAL := 3;  -- revision id, commit hash or id (hash: first 9 chars of the 40chars commit hash)
-  CONSTANT c_nof_design_note_regs : NATURAL := 13; -- note
+  CONSTANT c_nof_design_note_regs : NATURAL := 12; -- note
 
   CONSTANT c_info_reg             : NATURAL := 0;
   CONSTANT c_use_phy_reg          : NATURAL := 1;
@@ -87,7 +87,7 @@ ARCHITECTURE rtl OF unb2b_board_system_info_reg IS
   CONSTANT c_stamp_time_offset    : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + 1;
   CONSTANT c_revision_id_offset   : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
   CONSTANT c_design_note_offset   : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
-  CONSTANT c_nof_regs             : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs;
+  CONSTANT c_nof_regs             : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs; -- = 2+13+2+3+12 = 32
   CONSTANT c_mm_reg               : t_c_mem := (latency  => 1,
                                                 adr_w    => ceil_log2(c_nof_regs),
                                                 dat_w    => c_word_w,       -- Use MM bus data width = c_word_w = 32 for all MM registers

boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml

@@ -130,7 +130,7 @@ peripherals:
               access_mode: RO
           - - field_name: design_note
               field_description: "FPGA FW design note string."
-              number_of_fields: 52
+              number_of_fields: 48
               address_offset: 0x50
               mm_width: 32
               user_width: 8

boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd

@@ -78,7 +78,7 @@ ARCHITECTURE rtl OF unb2c_board_system_info_reg IS
   CONSTANT c_nof_design_name_regs : NATURAL := 13; -- design_name
   CONSTANT c_nof_stamp_regs       : NATURAL := 2;  -- date, time
   CONSTANT c_nof_revision_id_regs : NATURAL := 3;  -- revision id, commit hash or id (hash: first 9 chars of the 40chars commit hash)
-  CONSTANT c_nof_design_note_regs : NATURAL := 13; -- note
+  CONSTANT c_nof_design_note_regs : NATURAL := 12; -- note
 
   CONSTANT c_info_reg             : NATURAL := 0;
   CONSTANT c_use_phy_reg          : NATURAL := 1;
@@ -87,7 +87,7 @@ ARCHITECTURE rtl OF unb2c_board_system_info_reg IS
   CONSTANT c_stamp_time_offset    : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + 1;
   CONSTANT c_revision_id_offset   : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
   CONSTANT c_design_note_offset   : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
-  CONSTANT c_nof_regs             : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs;
+  CONSTANT c_nof_regs             : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs; -- = 2+13+2+3+12 = 32
   CONSTANT c_mm_reg               : t_c_mem := (latency  => 1,
                                                 adr_w    => ceil_log2(c_nof_regs),
                                                 dat_w    => c_word_w,       -- Use MM bus data width = c_word_w = 32 for all MM registers

boards/uniboard2c/libraries/unb2c_board/unb2c_board.peripheral.yaml

@@ -130,7 +130,7 @@ peripherals:
               access_mode: RO
           - - field_name: design_note
               field_description: "FPGA FW design note string."
-              number_of_fields: 52
+              number_of_fields: 48
               address_offset: 0x50
               mm_width: 32
               user_width: 8