From 337045b75010dd1d29c577931d642be01725a417 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Tue, 15 Mar 2022 16:45:04 +0100
Subject: [PATCH] decreased design_note field from 52B to 48B to fit the 32
word system info
---
.../unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd | 4 ++--
.../libraries/unb2b_board/unb2b_board.peripheral.yaml | 2 +-
.../unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd | 4 ++--
.../libraries/unb2c_board/unb2c_board.peripheral.yaml | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
index f7b14794bd..b6a3ffaa8b 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
@@ -78,7 +78,7 @@ ARCHITECTURE rtl OF unb2b_board_system_info_reg IS
CONSTANT c_nof_design_name_regs : NATURAL := 13; -- design_name
CONSTANT c_nof_stamp_regs : NATURAL := 2; -- date, time
CONSTANT c_nof_revision_id_regs : NATURAL := 3; -- revision id, commit hash or id (hash: first 9 chars of the 40chars commit hash)
- CONSTANT c_nof_design_note_regs : NATURAL := 13; -- note
+ CONSTANT c_nof_design_note_regs : NATURAL := 12; -- note
CONSTANT c_info_reg : NATURAL := 0;
CONSTANT c_use_phy_reg : NATURAL := 1;
@@ -87,7 +87,7 @@ ARCHITECTURE rtl OF unb2b_board_system_info_reg IS
CONSTANT c_stamp_time_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + 1;
CONSTANT c_revision_id_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
CONSTANT c_design_note_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
- CONSTANT c_nof_regs : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs;
+ CONSTANT c_nof_regs : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs; -- = 2+13+2+3+12 = 32
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_regs),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
diff --git a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
index fc5f4ccbf3..155cb99047 100644
--- a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
+++ b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
@@ -130,7 +130,7 @@ peripherals:
access_mode: RO
- - field_name: design_note
field_description: "FPGA FW design note string."
- number_of_fields: 52
+ number_of_fields: 48
address_offset: 0x50
mm_width: 32
user_width: 8
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
index 303690fe7c..504a41b01e 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
@@ -78,7 +78,7 @@ ARCHITECTURE rtl OF unb2c_board_system_info_reg IS
CONSTANT c_nof_design_name_regs : NATURAL := 13; -- design_name
CONSTANT c_nof_stamp_regs : NATURAL := 2; -- date, time
CONSTANT c_nof_revision_id_regs : NATURAL := 3; -- revision id, commit hash or id (hash: first 9 chars of the 40chars commit hash)
- CONSTANT c_nof_design_note_regs : NATURAL := 13; -- note
+ CONSTANT c_nof_design_note_regs : NATURAL := 12; -- note
CONSTANT c_info_reg : NATURAL := 0;
CONSTANT c_use_phy_reg : NATURAL := 1;
@@ -87,7 +87,7 @@ ARCHITECTURE rtl OF unb2c_board_system_info_reg IS
CONSTANT c_stamp_time_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + 1;
CONSTANT c_revision_id_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
CONSTANT c_design_note_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
- CONSTANT c_nof_regs : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs;
+ CONSTANT c_nof_regs : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs; -- = 2+13+2+3+12 = 32
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_regs),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
diff --git a/boards/uniboard2c/libraries/unb2c_board/unb2c_board.peripheral.yaml b/boards/uniboard2c/libraries/unb2c_board/unb2c_board.peripheral.yaml
index 067556ecde..804d7b4d86 100644
--- a/boards/uniboard2c/libraries/unb2c_board/unb2c_board.peripheral.yaml
+++ b/boards/uniboard2c/libraries/unb2c_board/unb2c_board.peripheral.yaml
@@ -130,7 +130,7 @@ peripherals:
access_mode: RO
- - field_name: design_note
field_description: "FPGA FW design note string."
- number_of_fields: 52
+ number_of_fields: 48
address_offset: 0x50
mm_width: 32
user_width: 8
--
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