Added g_sim, g_sim_level for tech_xaui. Also require...

Added g_sim, g_sim_level for tech_xaui. Also require txc_rx_channelaligned_arr()='1' for tx_snk_out_arr().xon.

libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd

@@ -58,6 +58,7 @@ USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
 ENTITY tech_eth_10g_stratixiv IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
+    g_sim_level           : NATURAL := 0;     -- 0 = use XAUI IP; 1 = use fast serdes model
     g_nof_channels        : NATURAL := 1;
     g_link_status_check   : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11";
     g_pre_header_padding  : BOOLEAN := FALSE
@@ -65,6 +66,7 @@ ENTITY tech_eth_10g_stratixiv IS
   PORT (
     -- Transceiver PLL reference clock
     tr_ref_clk_156   : IN  STD_LOGIC;   -- 156.25 MHz for XAUI
+    tr_ref_rst_156   : IN  STD_LOGIC;
     
     -- Calibration & reconfig clock
     cal_rec_clk      : IN  STD_LOGIC;
@@ -146,7 +148,7 @@ BEGIN
       IF rising_edge(tx_clk_arr(I)) THEN
         tx_snk_out_arr(I).xon <= '0';
         v_xgmii_link_status := xgmii_link_status_arr(I) AND g_link_status_check;  -- use mask to check Tx, Rx, both or none. 
-        IF xgmii_tx_ready_arr(I)='1' AND v_xgmii_link_status="00" THEN
+        IF xgmii_tx_ready_arr(I)='1' AND txc_rx_channelaligned_arr(I)='1' AND v_xgmii_link_status="00" THEN
           tx_snk_out_arr(I).xon <= '1';  -- XON when Tx PHY is ready and XGMII is ok
         END IF;
       END IF;
@@ -185,11 +187,14 @@ BEGIN
   u_tech_xaui: ENTITY tech_xaui_lib.tech_xaui
   GENERIC MAP (
     g_technology      => c_tech_stratixiv,
+    g_sim             => g_sim,
+    g_sim_level       => g_sim_level,
     g_nof_xaui        => g_nof_channels  -- Up to 3 (hard XAUI only) supported
   )
   PORT MAP (
     -- Transceiver PLL reference clock   
     tr_clk                    => tr_ref_clk_156,
+    tr_rst                    => tr_ref_rst_156,
 
     -- Calibration & reconfig clock
     cal_rec_clk               => cal_rec_clk,