hopefully better

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd

@@ -83,69 +83,53 @@ BEGIN
   q_reg <= d_reg WHEN rising_edge(clk);
 
   -- Increments the address each time in_sosi.valid = '1', if address = c_max_adr the address is reset to 0.
-  p_adr : PROCESS(rst, in_sosi)
+  p_adr : PROCESS(rst, in_sosi.valid)
 
   VARIABLE v              : t_reg                                 := c_t_reg_init;
 
   BEGIN
-    v.out_mosi.wrdata(c_data_w-1 DOWNTO 0)                      := in_sosi.data(c_data_w - 1 DOWNTO 0);
+    v.out_mosi.wrdata(c_data_w-1 DOWNTO 0)                        := in_sosi.data(c_data_w - 1 DOWNTO 0);
     v.out_mosi.wr                                                 := in_sosi.valid;
     v.out_of                                                      := in_of;
 
+    IF rst = '1' THEN
+      v.state := RESET;
+      assert false report "setting state to reset" severity note;
+    ELSIF v.out_mosi.address(c_adr_w-1 DOWNTO 0) = c_max_adr(c_adr_w-1 DOWNTO 0) AND in_sosi.valid = '1' THEN
+      v.state := MAX;
+      assert false report "setting state to max" severity note;
+    ELSIF in_sosi.valid = '1' THEN
+      v.state := COUNTING;
+      assert false report "setting state to counting" severity note;
+    ELSE
+      v.state := IDLE;
+      assert false report "setting state to idle" severity note;
+    END IF;
+
+
+    assert false report "starting case" severity note;
     CASE v.state IS
     WHEN RESET =>
+      assert false report "starting reset" severity note;
       v.out_mosi.address(c_adr_w-1 DOWNTO 0) := (OTHERS => '0');
 
-      IF rst = '1' THEN
-        v.state := RESET;
-      ELSIF v.out_mosi.address(c_adr_w-1 DOWNTO 0) = c_max_adr(c_adr_w-1 DOWNTO 0) AND in_sosi.valid = '1' THEN
-        v.state := MAX;
-      ELSIF in_sosi.valid = '1' THEN
-        v.state := COUNTING;
-      ELSE
-        v.state := IDLE;
-      END IF;
-
     WHEN COUNTING =>
+      assert false report "starting counting" severity note;
       v.out_mosi.address(c_adr_w-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UVEC(TO_UINT(v.out_mosi.address)+1, c_adr_w));
 
-      IF rst = '1' THEN
-        v.state := RESET;
-      ELSIF v.out_mosi.address(c_adr_w-1 DOWNTO 0) = c_max_adr(c_adr_w-1 DOWNTO 0) AND in_sosi.valid = '1' THEN
-        v.state := MAX;
-      ELSIF in_sosi.valid = '1' THEN
-        v.state := COUNTING;
-      ELSE
-        v.state := IDLE;
-      END IF;
-
     WHEN MAX =>
+      assert false report "starting max" severity note;
       v.out_mosi.address(c_adr_w-1 DOWNTO 0) := (OTHERS => '0');
 
-      IF rst = '1' THEN
-        v.state := RESET;
-      ELSIF v.out_mosi.address(c_adr_w-1 DOWNTO 0) = c_max_adr(c_adr_w-1 DOWNTO 0) AND in_sosi.valid = '1' THEN
-        v.state := MAX;
-      ELSIF in_sosi.valid = '1' THEN
-        v.state := COUNTING;
-      ELSE
-        v.state := IDLE;
-      END IF;
-
     WHEN IDLE =>
-
-      IF rst = '1' THEN
-        v.state := RESET;
-      ELSIF v.out_mosi.address(c_adr_w-1 DOWNTO 0) = c_max_adr(c_adr_w-1 DOWNTO 0) AND in_sosi.valid = '1' THEN
-        v.state := MAX;
-      ELSIF in_sosi.valid = '1' THEN
-        v.state := COUNTING;
-      ELSE
-        v.state := IDLE;
-      END IF;
+      assert false report "starting idle" severity note;
+      v.out_mosi.address(c_adr_w-1 DOWNTO 0) := q_reg.out_mosi.address(c_adr_w-1 DOWNTO 0);
+      assert false report "q_reg.out_mosi.address = " & NATURAL'image(TO_UINT(v.out_mosi.address)) severity note;
 
     END CASE;
-  d_reg <= v;
+    assert false report "ending case" severity note;
+
+    d_reg <= v;
   END PROCESS;
 
   -- fill outputs

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd

@@ -35,7 +35,7 @@ ENTITY tb_ddrctrl_address_counter IS
     
     g_tech_ddr                : t_c_tech_ddr    := c_tech_ddr4_8g_1600m;                    -- type of memory
     g_sim_model               : BOOLEAN         := TRUE;                                    -- determens if this is a simulation
-    g_sim_length              : NATURAL         := 152                                       -- determens the length of the duration of the test
+    g_sim_length              : NATURAL         := 52                                       -- determens the length of the duration of the test
 
   );
 END tb_ddrctrl_address_counter;
@@ -151,15 +151,15 @@ BEGIN
   p_verify_address : PROCESS
   BEGIN
     FOR I IN 0 TO c_adr_size-1 LOOP
-       WAIT UNTIL out_mosi.wr = '1';     
-      IF q_rst = '1' THEN
-        WAIT UNTIL out_mosi.wr = '1';
-      END IF;
       IF I >= q_lag_due_reset THEN
         ASSERT I-q_lag_due_reset              = TO_UINT(out_mosi.address)           REPORT "Wrong address, 1, I = " & NATURAL'image(I-q_lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address))              SEVERITY ERROR;
       ELSE
         ASSERT (I-q_lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address)           REPORT "Wrong address, 2, I = " & NATURAL'image((I-q_lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
       END IF;
+      WAIT UNTIL out_mosi.wr = '1';     
+      IF q_rst = '1' THEN
+        WAIT UNTIL out_mosi.wr = '1';
+      END IF;
     END LOOP;
   END PROCESS;