-init_dly_cnt is now triggered by a delayed version of the int_val signal.

libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd

@@ -102,6 +102,9 @@ begin
     
     if(r.val_dly(0) = '1') then                                 -- Wait for incoming data
       v.rd_addr := INCR_UVEC(r.rd_addr, 1);
+    end if;                                     
+
+    if(r.val_dly(c_tot_latency-2) = '1') then                                 -- Wait for incoming data
       if(r.init_dly_cnt < c_filter_zdly) then
         v.init_dly_cnt := r.init_dly_cnt + 1;
         v.out_val_ena := '0';