From 3318ea92e26228dd1a22831934a8f8921264eef7 Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Tue, 23 Jun 2015 13:45:04 +0000
Subject: [PATCH] -init_dly_cnt is now triggered by a delayed version of the
 int_val signal.

---
 libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd b/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd
index 4f0b80fa62..210ca23b79 100644
--- a/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd
@@ -102,6 +102,9 @@ begin
     
     if(r.val_dly(0) = '1') then                                 -- Wait for incoming data
       v.rd_addr := INCR_UVEC(r.rd_addr, 1);
+    end if;                                     
+
+    if(r.val_dly(c_tot_latency-2) = '1') then                                 -- Wait for incoming data
       if(r.init_dly_cnt < c_filter_zdly) then
         v.init_dly_cnt := r.init_dly_cnt + 1;
         v.out_val_ena := '0';
-- 
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