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Commit 3148327c authored by Eric Kooistra's avatar Eric Kooistra
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Finished draft design for SDP ring. Updated on SDP planning.

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applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt 100644 → 100755
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******************************************************************************* *******************************************************************************
* SDP Firmware planning * SDP Firmware planning
******************************************************************************* *******************************************************************************
Includes design, implementation, verification on HW, technical commissioning. Includes design, implementation, verification on HW, technical commissioning.
v1 v2 v1 v2
Infrastructure Infrastructure
10 20 - Development environment using GIT, RadioHDL, updating existing components 10 20 - Development environment using GIT, RadioHDL, updating existing components
20 . - BSP using Gemini Protocol, ARGS 20 . - BSP using Gemini Protocol, ARGS
10 . - Ethernet access (OSI 1-4) 10 . - Ethernet access (OSI 1-4)
10 20 - Ring access 10 20 - Ring access
Application: Application:
15 . - ADC ingress and time stamp 15 . - ADC ingress and time stamp
20 10 - Subband filterbank (critically sampled) 20 10 - Subband filterbank (critically sampled)
0 30 - Subband filterbank (oversampled) 0 30 - Subband filterbank (oversampled)
10 . - Beamformer 10 . - Beamformer
20 . - Subband correlator 20 . - Subband correlator
25 . - Transient buffer (DDR4 interface, subband select and DM >= 0, packet format, M&C, RW access via M&C) 25 . - Transient buffer (DDR4 interface, subband select and DM >= 0, packet format, M&C, RW access via M&C)
20 . - Transient detection 20 . - Transient detection
20 . - Subband offload 20 . - Subband offload
0 . - 160 MHz 0 . - 160 MHz
35 . Integration 35 . Integration
5 - FPGA pinning 5 - FPGA pinning
10 - Interface test designs unb2c 10 - Interface test designs unb2c
5 - Design revisions and lab tests 5 - Design revisions and lab tests
15 - Technical commissioning 15 - Technical commissioning
1 week = 100% project allocation, bruto 40 hours, netto 40 * 0.8 = 32 hours = 4 days 1 week = 100% project allocation, bruto 40 hours, netto 40 * 0.8 = 32 hours = 4 days
sprint = 100% project allocation, bruto 3 weeks, netto 12 days sprint = 100% project allocation, bruto 3 weeks, netto 12 days
v1 : 10 + 20 + 10 + 10 + 15 + 20 + 10 + 20 + 25 + 20 + 20 + 35 = 215 bruto weeks --> 215 / 40 = 5.4 FTE ~ 3 people each 2 years v1 : 10 + 20 + 10 + 10 + 15 + 20 + 10 + 20 + 25 + 20 + 20 + 35 = 215 bruto weeks --> 215 / 40 = 5.4 FTE ~ 3 people each 2 years
v2 : 10 less for critically sampled PFB v2 : 10 less for critically sampled PFB
10 more for updating existing components 10 more for updating existing components
10 more for ring access 10 more for ring access
30 for oversampled PFB 30 for oversampled PFB
. consider unb2c test part of SDP FW integration and of SDP HW . consider unb2c test part of SDP FW integration and of SDP HW
15 technical commisioning relies on proper Systems Engineering, otherwise may become 50 weeks 15 technical commisioning relies on proper Systems Engineering, otherwise may become 50 weeks
==> EK, JH: v1 estimate of April 2019 is still valid as v2 on 10 Oct 2019. ==> EK, JH: v1 estimate of April 2019 is still valid as v2 on 10 Oct 2019.
v3 : v3 :
Infrastructure Infrastructure
20 - Development environment using GIT, RadioHDL, updating existing components 20 - Development environment using GIT, RadioHDL, updating existing components
5 - unb2c FPGA pinning 5 - unb2c FPGA pinning
10 - unb2c FPGA interface test designs 10 - unb2c FPGA interface test designs
20 - Board Support Package using Gemini Protocol and ARGS 20 - Board Support Package using Gemini Protocol and ARGS
20 - Ring access 20 - Ring access
10 - 10GbE access (OSI 1-4) 10 - 10GbE access (OSI 1-4)
Application: Application:
15 - ADC input and time stamp 15 - ADC input and time stamp
10 - Subband filterbank (critically sampled) 10 - Subband filterbank (critically sampled)
20 - Subband correlator 20 - Subband correlator
10 - Beamformer 10 - Beamformer
25 - Transient buffer 25 - Transient buffer
20 - Subband offload for AARTFAAC 20 - Subband offload for AARTFAAC
20 - Transient detection 20 - Transient detection
30 - Oversampled subband filterbank 30 - Oversampled subband filterbank
0 - Support 160 MHz 0 - Support 160 MHz
Integration: Integration:
10 - Lab tests 10 - Lab tests
5 - Technical commissioning Dwingeloo 5 - Technical commissioning Dwingeloo
5 - Technical commissioning Prototype Station 5 - Technical commissioning Prototype Station
All: All:
20 + 5 + 10 + 20 + 20 + 10 + 15 + 10 + 20 + 10 + 25 + 20 + 20 + 30 + 0 + 10 + 5 + 5 = 255 20 + 5 + 10 + 20 + 20 + 10 + 15 + 10 + 20 + 10 + 25 + 20 + 20 + 30 + 0 + 10 + 5 + 5 = 255
No oversampled filterbank: No oversampled filterbank:
20 + 5 + 10 + 20 + 20 + 10 + 15 + 10 + 20 + 10 + 25 + 20 + 20 + 0 + 10 + 5 + 5 = 225 20 + 5 + 10 + 20 + 20 + 10 + 15 + 10 + 20 + 10 + 25 + 20 + 20 + 0 + 10 + 5 + 5 = 225
******************************************************************************* *******************************************************************************
* SDP Workpackage (UniBoard2 HW + FW) * SDP Workpackage (UniBoard2 HW + FW)
******************************************************************************* *******************************************************************************
Firmware FPGA images: Changed tasks:
- the SDP has one main firmware design unb2c_sdp, - T4.6 : 20 weeks booked explicitely for Required documents
- the integrated design of SDP is revision unb2c_sdp_station, - T4.1 : 10 weeks, because GIT, RadioHDL finished
- per task there are revisions of unb2c_sdp that contain subsets of the SDP functionality, - T4.2 : 10 weeks, because some FW done
- T4.2 : ? weeks, hardware effort
Deliverables (D): items that are needed for a milestone
Milestones (M) : 'cake moments' when you demonstrate deliverables Firmware FPGA images:
- integration passed - the SDP has one main firmware design unb2c_sdp,
- review passed - the integrated design of SDP is revision unb2c_sdp_station,
- per task there are revisions of unb2c_sdp that contain subsets of the SDP functionality,
Tasks:
Deliverables (D) = an item, product : items that are needed for a milestone
INFRASTRUCTURE UniBoard2: Milestones (M) = a moment in time, achievement : 'cake moments' when you demonstrate or review
weeks nr task deliverables as part of a larger system
20 1) Maintain firmware development environment - integration passed
- using GIT - review passed
- using RadioHDL
- updating existing VHDL library components Planning for LOFAR2.0 Station Workpackage 4 : Station Digital Processing
D=> Operational firmware development environment
D=> VHDL libraries verified in simulation Below is the planning in weeks per task, the work includes:
- UniBoard2 hardware
2) UniBoard2 board and test firmware - Firmware that runs on UniBoard2
- unb2c board HW
D=> unb2c board detailed design document weeks task description
D=> unb2c board schematic 10 T4.1 Maintain firmware development environment (GIT, RadioHDL, HDL libraries)
D=> unb2c board layout 10 T4.2 UniBoard2 test firmware (enable mass production of UniBoard2)
? T4.2 UniBoard2 board hardware
M=> unb2c board detailed design document review (unb2b modifications) 20 T4.3 UniBoard2 board support package (BSP, M&C via Gemini Protocol, use ARGS for doc, C, VHDL)
M=> unb2c board schematic review 10 T4.4 Network access via 10GbE (support ARP and ping)
M=> unb2c board layout review (production ready) 20 t4.5 Ring access using test data and BSN monitor (support ring)
M=> unb2c board lab validation using JTAG, unb2c_test designs OK 20 T4.6 Required documents (SDP RS, detailed design, ICDs, FW manual)
M=> unb2c board production validation using JTAG, unb2c_minimal_gmi OK 15 T4.7 ADC input and timestamp (RCU2 interface, capture timestamped data for offline analysis)
10 T4.8 Subband filterbank (Fsub, critically sampled, SST)
5 - unb2c FPGA pinning design 20 T4.9 Subband correlator (XC, one subband per 1 s integration)
10 - unb2c FPGA interface test designs 10 T4.10 Beamformer (BF, BST, beamlet output to CEP)
D=> unb2c_test design revisions (1GbE, 10GbE, DDR4, flash, ADC)
D=> unb2c_test_adc (read ADC samples from multiple inputs) 10 + 10 + ? + 20 + 10 + 20 + 20 + 15 + 10 + 20 + 10 = 145 + ? weeks
Milestone : SDP ready for CDR:
20 3) UniBoard2 board support package (BSP) All major technical UniBoard2 hardware and SDP firmware risks are mitigated:
- M&C by SCU via Gemini protocol
- M&C interface definition and generation using ARGS (doc, C, HDL) - by design
D=> Gemini board for SCU M&C tests - SDP hardware and interfaces validated with at least two UniBoard2 using JTAG, firmware for BSP,
D=> unb2c_minimal_gmi (1GbE, flash) ring and ADC
M=> unb2c_minimal_gmi validated using M&C by SCU (read design name) - Station TD validated using BF beamlet output to CEP
INFRASTRUCTURE SDP: The remaining tasks concern completing the applications that the firmware needs to perform.
10 4) Network access via 10GbE
- Ethernet MAC, UDP/IPv4, ARP, ping weeks task description
D=> 10GbE HDL component including support for UDP/IPv4, ARP, ping 25 T4.11 Transient buffer (TB, ADC data, subband data)
D=> unb2c_10GbE 20 T4.12 Transient detection (TDET)
M=> unb2c_10GbE validated using data capture on PC and ping 20 T4.13 Subband offload (SO) for AARTFAAC2.0
20 T4.14 Station integration tests (using unb2c_sdp_station)
20 5) Ring access using test data and BSN monitor
D=> unb2c_ring_combiner for BF 25 + 20 + 20 + 20 = 85 weeks
D=> unb2c_ring_multicast for XC
D=> unb2c_ring_endcast for SO, TB
M=> unb2c_ring revisions verified in simulation
M=> unb2c_ring revisions validated on hardware using M&C on SCU
APPLICATION SDP documents:
6) Required documents
D=> Detailed design document of SDP firmware
D=> L1 ICD-11109 SDP-CEP: beamlet data protocol
D=> L1 ICD-11109 SDP-CEP: transient data protocol
D=> L2 ICD-11211 SC-SDP: FW register map and register definitions
D=> L2 ICD-11211 SC-SDP: UniBoard2 hardware M&C
D=> L2 ICD-11207 RCU2S-SDP: ADC interface
D=> L2 ICD-11209 STF-SDP: Time and frequency interface
D=> L2 ICD-11218 SDP-STCA: Subrack interface
M=> SDP detailed design and interface documents ready for DDR
M=> SDP detailed design and interface documents updated for CDR
D=> SDP firmware verification and maintenance document
M=> SDP all documents finished
APPLICATION single node:
weeks nr task
15 7) ADC input and timestamp (RCU2 interface)
==> unb2c_sdp_adc_capture, read ADC or WG samples from databuffer via M&C
==> unb2c_sdp_station (ADC)
M=> SDP ready for CDR
All major technical UniBoard2 hardware and SDP firmware risks are mitigated (by design and
based on validation with at least two UniBoard2 using JTAG, unb2c_minimal_gmi, unb2c_ring,
and unb2c_sdp_adc_capture).
10 8) Subband filterbank (Fsub)
==> unb2c_sdp_filterbank to read SST via M&C
==> unb2c_sdp_station (ADC + SST)
APPLICATION multi node:
weeks nr task
20 9) Subband correlator (XC)
==> unb2c_sdp_correlator_one_node, read XST via M&C and create ACM for one node
==> unb2c_sdp_correlator_multi_node, read XST via M&C and use ring to create complete ACM
==> unb2c_sdp_station (ADC + SST + XST)
APPLICATION multi node / network output:
weeks nr task
10 10) Beamformer (BF)
==> unb2c_sdp_beamformer_bst_one_node, read BST via M&C
==> unb2c_sdp_beamformer_output_one_input, output to CEP for one input from one node
==> unb2c_sdp_beamformer_output_one_node, output to CEP and sum one node
==> unb2c_sdp_beamformer_output_multi_node, output to CEP and use ring to sum nodes
==> unb2c_sdp_station (ADC + SST + XST + BST + BF output)
==> detailed design doc
25 11) Transient buffer (TB)
==> unb2c_sdp_transient_buffer revisions (ADC + SST + TB readout, M&C access DDR4)
==> unb2c_sdp_station (ADC + SST + XST + BST + BF output + TB readout)
==> detailed design doc
20 12) Transient detection (TD)
==> unb2c_sdp_transient_buffer revisions (ADC + TD event)
==> unb2c_sdp_station (ADC + SST + XST + BST + BF output + TB readout + TD event)
==> detailed design doc
20 13) Subband offload (SO) for AARTFAAC2.0
==> unb2c_sdp_subband_offload revisions (ADC + SST + SO, one node, all nodes via ring)
==> unb2c_sdp_station (ADC + SST + XST + BST + BF output + TB readout + TD event + SO)
==> detailed design doc
INTEGRATION:
weeks nr task
20 14) Station integration tests (using unb2c_sdp_station)
- Laboratory tests
- Technical commissioning Dwingeloo Test Station ("Huisje West")
- Technical commissioning Prototype Test Station
- Technical commissioning Pre-production Test Station
applications/lofar2/doc/prestudy/station2_sdp_ring.txt
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applications/lofar2/doc/prestudy/station2_to_do_erko.txt
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...@@ -227,6 +227,9 @@ Open issues: ...@@ -227,6 +227,9 @@ Open issues:
- Write RadioHDL article - Write RadioHDL article
- Write HDL RL=0 article - desp_hdl_design_article.txt - Write HDL RL=0 article - desp_hdl_design_article.txt
- XST : SNR = 1 per visibility for 10000 samples, brigthtest sourcre log 19.5 --> 4.5 dB --> T_int = 1 s is ok. - XST : SNR = 1 per visibility for 10000 samples, brigthtest sourcre log 19.5 --> 4.5 dB --> T_int = 1 s is ok.
- BSP registers:
. duration of operations : counts time since last power cycle (passive heartbeat)
. cause of reboot (power cycle, overtemperature, ...)
......
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