changed the ready signal to be used to the actual DUT output.

libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd

@@ -254,7 +254,7 @@ BEGIN
   proc_dp_verify_block_size(exp_size, clk, verify_snk_in.valid, verify_snk_in.sop, verify_snk_in.eop, cnt_size);
   
   -- Verify output ready latency
-  proc_dp_verify_valid(clk, verify_en_valid, verify_snk_out.ready, prev_verify_snk_out.ready, verify_snk_in.valid);
+  proc_dp_verify_valid(clk, verify_en_valid, stimuli_src_in.ready, prev_verify_snk_out.ready, verify_snk_in.valid);
   
   p_verify_xonoff : PROCESS
     VARIABLE vI : INTEGER := 0;