. FPGA_tbuf_record_all_antenna_RW[pn] # True = record all antenna inputs, False = record only half of the antenna inputs, the once that have even index.
. W_adc = 14b, always use all ADC bits, so no need for W_raw.
. W_ant = N_pol * W_adc = 28b
. c_tbuf_raw_sample_period
= 5 ns at FPGA_sdp_info_f_adc_R = 200 MHz
= 6.25 ns at FPGA_sdp_info_f_adc_R = 160 MHz
* RSN source (dp_rsn_source with nof_clk_per_sync register)
FPGA_processing_enable_RW
. SDPTR: set tbuf_nof_clk_per_sync dependent on FPGA_sdp_info_f_adc_R
. SDPFW: start RSN source at BSN sync, RSN derived from BSN
False is ddr4 calibration failed or ddr4 not present.
. FPGA_ddr_wr_fifo_full_R = wr_fifo_full_reg, True if write FIFO to ddr4 memory got full since last MP read, else False. Should remain False.
. FPGA_ddr_wr_fifo_full_R = wr_fifo_full_reg, True if write FIFO to ddr4 memory got full since last MP read, else False. Should remain False.
. FPGA_ddr_rd_fifo_full_R = rd_fifo_full_reg, True if read FIFO from ddr4 memory got full since last MP read, else False. Should remain False.
. FPGA_ddr_rd_fifo_full_R = rd_fifo_full_reg, True if read FIFO from ddr4 memory got full since last MP read, else False. Should remain False.
. FPGA_ddr_wr_fifo_usedw_R = ctlr_wr_fifo_usedw, current fill level of write FIFO to ddr4 memory in number of 512b words, should be 0 when not recording
. FPGA_ddr_wr_fifo_usedw_R = ctlr_wr_fifo_usedw, current fill level of write FIFO to ddr4 memory in number of 512b words, should be 0 when not recording
. FPGA_ddr_rd_fifo_usedw_R = ctlr_rd_fifo_usedw, current fill level of read FIFO from ddr4 memory in number of 512b words, should be 0 when not dumping
. FPGA_ddr_rd_fifo_usedw_R = ctlr_rd_fifo_usedw, current fill level of read FIFO from ddr4 memory in number of 512b words, should be 0 when not dumping
There is no MP for drv_miso.done, could show hanging io_ddr_driver. All other fields in drv_miso are unused ('X').
No need for CP of:
No need for CP of:
- dvr_wr_flush_en, because io_ddr and DDR4 should work without need to flush when they operate OK.
- dvr_wr_flush_en, because io_ddr and DDR4 should work without need to flush when they operate OK.
No need to MP for:
No need to MP for:
- ctlr_tech_mosi.wr, because controlled by streaming sequencer
- ctlr_tech_mosi.wr, because controlled by streaming sequencer
- ctlr_rst_out_i, because also used as reset for io_ddr itself
- ctlr_rst_out_i, because also used as reset for io_ddr itself
- ctlr_tech_miso.waitrequest_n ? could show hanging io_ddr_driver
- ctlr_tech_miso.waitrequest_n ? could show hanging io_ddr_driver or refresh cycles
- ctlr_tech_miso.done ? could show hanging io_ddr_driver
* Memory buffer:
REG_TBUF_RAW new in node_sdp_transient_buffer_raw.vhd
REG_TBUF_RAW new in node_sdp_transient_buffer_raw.vhd
. nof_bytes_in_ddr_R = 16 * 1024**3 (16GiB)
. record_all_RW
. nof_bytes_per_ddr_word_R = 64 Bytes (= 512b)
True = record all antenna inputs,
. nof_ddr_words_per_page_R = 657 or 329, depends on FPGA_tbuf_record_all_antenna_RW
False = record only half of the antenna inputs, the once that have even index.
