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applications/lofar2/libraries/ddrctrl/src/vhdl/address_counter.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: Job van Wee
+-- Purpose: Create address by counting input valids
+--
+-- Description:
+--  The counter starts on the first valid = '1' clockcylce, the counter stops 
+--  when valid = '0'.
+--
+-- Remark:
+--  Use VHDL coding template from:
+--  https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
+--  The maximum value of the address is determend by g_tech_ddr.
+
+
+
 LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
@@ -37,7 +70,7 @@ BEGIN
   BEGIN
     IF rising_edge(clk) THEN
       IF rst = '1' THEN
-        s_adr <= 0;                                                            -- https://stackoverflow.com/questions/9989913/vhdl-how-to-use-clk-and-reset-in-process
+        s_adr <= 0;
       ELSIF in_sosi.valid = '1' THEN
         IF (s_adr = 2**(c_adr_w) - 1) THEN
           s_adr <= 0;

applications/lofar2/libraries/ddrctrl/src/vhdl/pack.vhd

-LIBRARY IEEE, dp_lib;
-USE IEEE.std_logic_1164.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-
-ENTITY pack IS
-  GENERIC (
-    g_nof_streams	: POSITIVE := 12;
-    g_data_w		: NATURAL  := 14
-  );
-  PORT (
-    clk	      	: IN  STD_LOGIC;
-    in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
-    out_data 	: OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0)
-  );
-END pack;
-
-ARCHITECTURE rtl OF pack IS
-
-BEGIN
-
-  gen_extract_and_pack_data : FOR I IN 0 TO g_nof_streams-1 GENERATE
-    out_data(g_data_w*(I+1)-1 DOWNTO g_data_w*I) <= in_sosi_arr(I).data(g_data_w-1 DOWNTO 0);
-  END GENERATE;
-
-END rtl;

applications/lofar2/libraries/ddrctrl/src/vhdl/repack.vhd

-LIBRARY IEEE, dp_lib;
-USE IEEE.std_logic_1164.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-
-ENTITY repack IS
-  GENERIC (
-    g_in_data_w	  : NATURAL := 168;
-    g_out_data_w  : NATURAL := 576
-  );
-  PORT (
-    clk	     	    : IN  STD_LOGIC;
-    out_o_f     	: OUT NATURAL;
-    in_data  	    : IN  STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0);
-    out_sosi      : OUT t_dp_sosi
-  );
-END repack;
-
-
-ARCHITECTURE rtl OF repack IS
-
-  CONSTANT k_c_v_w			    : NATURAL := g_out_data_w*2;
-
-  SIGNAL  c_v_count			    : NATURAL := 0;
-  SIGNAL  out_data_count		: NATURAL := 0;
-  SIGNAL  a_o_f 			      : NATURAL := 0;
-  SIGNAL  c_v				        : STD_LOGIC_VECTOR (k_c_v_w-1 DOWNTO 0);
-
-BEGIN
-
-  p_clk : PROCESS(clk)
-  BEGIN
-
-    IF rising_edge(clk) THEN
-
-      IF (g_in_data_w*(c_v_count+1) >= g_out_data_w*(out_data_count+1)) THEN								                                          	-- if the input data exceeds the output data vector width
-
-	      IF (out_data_count = 1) THEN													                                                                         	-- if the input data exceeds c_v vector widt
-	        out_o_f <= a_o_f;													                                                                                 		-- set the output overflow to the overflow that maches the out_sosi.data vector
-          a_o_f <= a_o_f + g_in_data_w * c_v_count - g_out_data_w * (out_data_count + 1);							                                  -- check how much overflow there is and safe it in a_o_f
-	        c_v(k_c_v_w - 1 DOWNTO k_c_v_w - (g_in_data_w - a_o_f)) <= in_data(g_in_data_w - a_o_f - 1 DOWNTO 0);			                    -- fill the rest of c_v untill the end
-	        c_v(a_o_f - 1 DOWNTO 0) <= in_data(g_in_data_w - 1 DOWNTO g_in_data_w - a_o_f);							                                  -- fill the start of c_v untill the a_o_f
-	        out_sosi.data(g_out_data_w - 1 DOWNTO 0) <= c_v(k_c_v_w - 1 DOWNTO g_out_data_w);							                                -- fill out_sosi.data with 2nd part of c_v
-	        out_sosi.valid <= '1';													                                                          	                  -- out_sosi.valid 1
-	        c_v_count	<= 0; 													                                                                                   	-- reset counter
-          out_data_count <= 0;													                                                                               	-- reset counter
-
-	      Else															                                                                                            	-- if the input data exceeds output data vector width but not the c_v vector widt
-	        c_v(g_in_data_w * (c_v_count + 1) + a_o_f - 1 DOWNTO g_in_data_w * c_v_count + a_o_f) <= in_data(g_in_data_w - 1 DOWNTO 0); 	-- fill c_v
-	        c_v_count <= c_v_count + 1;													                                                                          -- increase the counter of c_v with 1
-	        out_sosi.data(g_out_data_w - 1 DOWNTO 0) <= c_v(g_out_data_w - 1 DOWNTO 0);						                                        -- fill out_sosi.data with 1st part of c_v
-	        out_data_count <= out_data_count + 1;													                                                                -- increase the counter of out_sosi.data with 1
-	        out_sosi.valid <= '1';													                                                                              -- out_sosi.valid 1
-
-	      END IF;
-
-      ELSE															                                                                                              	-- if the input data doesn't exceeds the output data vector width
-	      c_v(g_in_data_w * (c_v_count + 1) + a_o_f - 1 DOWNTO g_in_data_w * c_v_count + a_o_f) <= in_data(g_in_data_w - 1 DOWNTO 0);	    -- fill c_v
-	      c_v_count <= c_v_count + 1;														                                                                        	-- increase the counter of c_v with 1
-        out_sosi.valid <= '0';														                                                                              -- out_sosi.valid 0
-
-      END IF;
-
-    END IF;
-
-  END PROCESS;
-
-END rtl;
-
-

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_address_counter.vhd

---------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
 --
--- Copyright (C) 2011
+-- Copyright 2022
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+--     http://www.apache.org/licenses/LICENSE-2.0
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
 --
---------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Author: Job van Wee
+-- Purpose: Self checking and self-stopping tb for address_counter.vhd
+-- Usage:
+-- > run -a
 
 LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib, dp_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE IEEE.MATH_REAL.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE tech_ddr_lib.tech_ddr_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
@@ -56,9 +56,6 @@ ARCHITECTURE tb OF tb_address_counter IS
   SIGNAL    in_data_enable    : STD_LOGIC;
   SIGNAL    in_sosi           : t_dp_sosi       := c_dp_sosi_init;
 
-  SIGNAL    out_data          : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
-  SIGNAL    out_data_enable   : STD_LOGIC;
-  SIGNAL    adr               : NATURAL RANGE 0 TO 2**(c_adr_w)-1 := 0;
   SIGNAL    out_mosi          : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst;
 
 BEGIN
@@ -66,9 +63,7 @@ BEGIN
   in_sosi.data(c_data_w - 1 DOWNTO 0)    <= in_data(c_data_w - 1 DOWNTO 0);
   in_sosi.valid                          <= in_data_enable;
 
-  out_data(c_data_w - 1 DOWNTO 0)        <= out_mosi.wrdata(c_data_w - 1 DOWNTO 0);
-  out_data_enable                        <= out_mosi.wr;
-  adr                                    <= TO_UINT(out_mosi.address);
+
 
 
   clk <= NOT clk OR tb_end AFTER c_clk_period/2;
@@ -85,64 +80,27 @@ BEGIN
     WAIT UNTIL rising_edge(clk);  -- align to rising edge
     WAIT FOR c_clk_period*10;
 
+    FOR I IN 0 TO 6 LOOP
       in_data_enable    <= '1';
       in_data           <= NOT in_data;
+      ASSERT in_data(c_data_w - 1 DOWNTO 0) = out_mosi.wrdata(c_data_w - 1 DOWNTO 0) REPORT "Wrong wrdata 1"  SEVERITY ERROR;
+      ASSERT in_data_enable                 = out_mosi.wr                            REPORT "Wrong wr 1"      SEVERITY ERROR;
+      ASSERT I                              = TO_UINT(out_mosi.address)              REPORT "Wrong address 1" SEVERITY ERROR;
       WAIT FOR c_clk_period*1;
       in_data_enable    <= '0';
       WAIT FOR c_clk_period*2;
+    END LOOP;
 
-    in_data_enable    <= '1';
-    in_data           <= NOT in_data;
-    WAIT FOR c_clk_period*1;
-    in_data_enable    <= '0';
-    WAIT FOR c_clk_period*2;
-
-    in_data_enable    <= '1';
-    in_data           <= NOT in_data;
-    WAIT FOR c_clk_period*1;
-    in_data_enable    <= '0';
-    WAIT FOR c_clk_period*2;
-
-    in_data_enable    <= '1';
-    in_data           <= NOT in_data;
-    WAIT FOR c_clk_period*1;
-    in_data_enable    <= '0';
-    WAIT FOR c_clk_period*2;
-
-    in_data_enable    <= '1';
-    in_data           <= NOT in_data;
-    WAIT FOR c_clk_period*1;
-    in_data_enable    <= '0';
-    WAIT FOR c_clk_period*2;
-
-    in_data_enable    <= '1';
-    in_data           <= NOT in_data;
-    WAIT FOR c_clk_period*1;
-    in_data_enable    <= '0';
-    WAIT FOR c_clk_period*2;
-
-    in_data_enable    <= '1';
-    in_data           <= NOT in_data;
     WAIT FOR c_clk_period*1;
     rst               <= '1';               -- reset
-    in_data_enable    <= '0';
     WAIT FOR c_clk_period*1;
     rst               <= '0';
     WAIT FOR c_clk_period*1;
 
-    in_data_enable    <= '1';
-    in_data           <= NOT in_data;
-    WAIT FOR c_clk_period*1;
-    in_data_enable    <= '0';
-    WAIT FOR c_clk_period*2;
-
-    in_data_enable    <= '1';
-    in_data           <= NOT in_data;
-    WAIT FOR c_clk_period*1;
-    in_data_enable    <= '0';
-    WAIT FOR c_clk_period*2;
-
-    WHILE (adr /= 1) LOOP
+    FOR I IN 0 TO 20 LOOP
+      ASSERT in_data(c_data_w - 1 DOWNTO 0) = out_mosi.wrdata(c_data_w - 1 DOWNTO 0) REPORT "Wrong wrdata 2"  SEVERITY ERROR;
+      ASSERT in_data_enable                 = out_mosi.wr                            REPORT "Wrong wr 2"      SEVERITY ERROR;
+      ASSERT I = TO_UINT(out_mosi.address) OR I - 16 = TO_UINT(out_mosi.address)     REPORT "Wrong address, I = " & NATURAL'image(I)  SEVERITY ERROR;
       in_data_enable    <= '1';
       in_data           <= NOT in_data;
       WAIT FOR c_clk_period*1;