corrected nof_dat 3**2 -> 2**3

libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd

@@ -82,7 +82,7 @@ ARCHITECTURE rtl OF dp_bsn_source_reg_v2 IS
   CONSTANT c_mm_reg : t_c_mem := (latency  => 1,
                                   adr_w    => 3,
                                   dat_w    => c_word_w,  -- Use MM bus data width = c_word_w = 32 for all MM registers
-                                  nof_dat  => 3**2,
+                                  nof_dat  => 2**3,
                                   init_sl  => '0');
   
   -- Registers in mm_clk domain