Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
H
HDL
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Container registry
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
RTSD
HDL
Commits
2e508353
Commit
2e508353
authored
9 years ago
by
Pepping
Browse files
Options
Downloads
Patches
Plain Diff
Added common_peak to detect and hold max value of used words.
Updated comments
parent
530571a0
Branches
Branches containing commit
No related tags found
No related merge requests found
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
+40
-11
40 additions, 11 deletions
libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
with
40 additions
and
11 deletions
libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
+
40
−
11
View file @
2e508353
...
@@ -19,24 +19,34 @@
...
@@ -19,24 +19,34 @@
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Purpose: Provide MM slave register for dp_
bsn_align
-- Purpose: Provide MM slave register for dp_
fifo_fill
-- Description:
-- Description:
--
--
-- Read/Write registers for all streams. The number of registers dpen
e
ds on the
-- Read/Write registers for all streams. The
total
number of registers d
e
pends on the
-- g_nof_
input
s that are used. Each
input has it's own enable
register
.
-- g_nof_
stream
s that are used. Each
stream has c_nof_regs_per_stream = 3
register
s.
--
--
-- 31 24 23 16 15 8 7 0 wi
-- 31 24 23 16 15 8 7 0 wi
-- |-----------------|-----------------|-----------------|-----------------|
-- |-----------------|-----------------|-----------------|-----------------|
-- |
enable_input0 = [0]
| 0
-- |
fifo_used_words stream 0
| 0
-- |-----------------------------------------------------------------------|
-- |-----------------------------------------------------------------------|
-- |
enable_input1 = [0]
| 1
-- |
wr_fifo_full = [1] rd_fifo_empty = [0] stream 0
| 1
-- |-----------------------------------------------------------------------|
-- |-----------------------------------------------------------------------|
-- | enable_input2 = [0] | 2
-- | max_fifo_used_words stream 0 | 2
-- |-----------------------------------------------------------------------|
-- | fifo_used_words stream 1 | 3
-- |-----------------------------------------------------------------------|
-- | wr_fifo_full = [1] rd_fifo_empty = [0] stream 1 | 4
-- |-----------------------------------------------------------------------|
-- | max_fifo_used_words stream 1 | 5
-- |-----------------------------------------------------------------------|
-- |-----------------------------------------------------------------------|
-- |
-- |
-- |
-- |
-- |-----------------------------------------------------------------------|
-- |-----------------------------------------------------------------------|
-- | enable_input.. = [0] | g_nof_inputs-1
-- | fifo_used_words stream x |
-- |-----------------------------------------------------------------------|
-- | wr_fifo_full = [1] rd_fifo_empty = [0] stream x |
-- |-----------------------------------------------------------------------|
-- | max_fifo_used_words stream x |
-- |-----------------------------------------------------------------------|
-- |-----------------------------------------------------------------------|
...
@@ -71,7 +81,8 @@ END dp_fifo_fill_reg;
...
@@ -71,7 +81,8 @@ END dp_fifo_fill_reg;
ARCHITECTURE
str
OF
dp_fifo_fill_reg
IS
ARCHITECTURE
str
OF
dp_fifo_fill_reg
IS
CONSTANT
c_nof_regs_per_stream
:
NATURAL
:
=
2
;
CONSTANT
c_reg_max_used_words_offset
:
NATURAL
:
=
2
;
CONSTANT
c_nof_regs_per_stream
:
NATURAL
:
=
3
;
-- Define the actual size of the MM slave register
-- Define the actual size of the MM slave register
CONSTANT
c_mm_reg
:
t_c_mem
:
=
(
latency
=>
1
,
CONSTANT
c_mm_reg
:
t_c_mem
:
=
(
latency
=>
1
,
...
@@ -84,12 +95,14 @@ ARCHITECTURE str OF dp_fifo_fill_reg IS
...
@@ -84,12 +95,14 @@ ARCHITECTURE str OF dp_fifo_fill_reg IS
SIGNAL
in_arr_reg
:
STD_LOGIC_VECTOR
(
g_nof_streams
*
c_nof_regs_per_stream
*
c_word_w
-1
DOWNTO
0
)
:
=
(
OTHERS
=>
'0'
);
SIGNAL
in_arr_reg
:
STD_LOGIC_VECTOR
(
g_nof_streams
*
c_nof_regs_per_stream
*
c_word_w
-1
DOWNTO
0
)
:
=
(
OTHERS
=>
'0'
);
SIGNAL
reg_wr_arr
:
STD_LOGIC_VECTOR
(
g_nof_streams
*
c_nof_regs_per_stream
-1
DOWNTO
0
)
:
=
(
OTHERS
=>
'0'
);
SIGNAL
reg_wr_arr
:
STD_LOGIC_VECTOR
(
g_nof_streams
*
c_nof_regs_per_stream
-1
DOWNTO
0
)
:
=
(
OTHERS
=>
'0'
);
SIGNAL
reg_rd_arr
:
STD_LOGIC_VECTOR
(
g_nof_streams
*
c_nof_regs_per_stream
-1
DOWNTO
0
)
:
=
(
OTHERS
=>
'0'
);
SIGNAL
reg_rd_arr
:
STD_LOGIC_VECTOR
(
g_nof_streams
*
c_nof_regs_per_stream
-1
DOWNTO
0
)
:
=
(
OTHERS
=>
'0'
);
SIGNAL
peak_used_w
:
STD_LOGIC_VECTOR
(
g_nof_streams
*
c_word_w
-1
DOWNTO
0
)
:
=
(
OTHERS
=>
'0'
);
BEGIN
BEGIN
gen_in_arr_reg
:
FOR
I
IN
0
TO
g_nof_streams
-1
GENERATE
gen_in_arr_reg
:
FOR
I
IN
0
TO
g_nof_streams
-1
GENERATE
in_arr_reg
((
2
*
I
+
1
)
*
c_word_w
-1
DOWNTO
2
*
I
*
c_word_w
)
<=
used_w
((
I
+
1
)
*
c_word_w
-1
DOWNTO
I
*
c_word_w
);
in_arr_reg
((
c_nof_regs_per_stream
*
I
+
1
)
*
c_word_w
-1
DOWNTO
c_nof_regs_per_stream
*
I
*
c_word_w
)
<=
used_w
((
I
+
1
)
*
c_word_w
-1
DOWNTO
I
*
c_word_w
);
in_arr_reg
((
2
*
I
+
1
)
*
c_word_w
+
1
DOWNTO
(
2
*
I
+
1
)
*
c_word_w
)
<=
wr_ful
(
I
)
&
rd_emp
(
I
);
in_arr_reg
((
c_nof_regs_per_stream
*
I
+
2
)
*
c_word_w
-31
DOWNTO
(
c_nof_regs_per_stream
*
I
+
1
)
*
c_word_w
)
<=
wr_ful
(
I
)
&
rd_emp
(
I
);
in_arr_reg
((
c_nof_regs_per_stream
*
I
+
3
)
*
c_word_w
-1
DOWNTO
(
c_nof_regs_per_stream
*
I
+
2
)
*
c_word_w
)
<=
peak_used_w
((
I
+
1
)
*
c_word_w
-1
DOWNTO
I
*
c_word_w
);
END
GENERATE
;
END
GENERATE
;
u_reg
:
ENTITY
common_lib
.
common_reg_r_w_dc
u_reg
:
ENTITY
common_lib
.
common_reg_r_w_dc
...
@@ -120,5 +133,21 @@ BEGIN
...
@@ -120,5 +133,21 @@ BEGIN
out_new
=>
OPEN
out_new
=>
OPEN
);
);
gen_peak_meters
:
FOR
I
IN
0
TO
g_nof_streams
-1
GENERATE
u_peak_meter
:
ENTITY
common_lib
.
common_peak
GENERIC
MAP
(
g_dat_w
=>
c_word_w
)
PORT
MAP
(
rst
=>
st_rst
,
clk
=>
st_clk
,
in_dat
=>
used_w
((
I
+
1
)
*
c_word_w
-1
DOWNTO
I
*
c_word_w
),
in_val
=>
'1'
,
in_clear
=>
reg_rd_arr
(
I
*
c_nof_regs_per_stream
+
c_reg_max_used_words_offset
),
out_dat
=>
peak_used_w
((
I
+
1
)
*
c_word_w
-1
DOWNTO
I
*
c_word_w
),
out_val
=>
OPEN
);
END
GENERATE
;
END
str
;
END
str
;
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment