diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
index 29ee7d89a9e10248e5c631a8e61123d89bed6e27..dff5af7b8365a63db60e354ca2b4a3830eadc932 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
@@ -19,24 +19,34 @@
 --
 -------------------------------------------------------------------------------
 
--- Purpose: Provide MM slave register for dp_bsn_align
+-- Purpose: Provide MM slave register for dp_fifo_fill
 -- Description:
 --
---  Read/Write registers for all streams. The number of registers dpeneds on the
---  g_nof_inputs that are used. Each input has it's own enable register.
+--  Read/Write registers for all streams. The total number of registers depends on the
+--  g_nof_streams that are used. Each stream has c_nof_regs_per_stream = 3 registers. 
 --
 --   31             24 23             16 15              8 7               0  wi
 --  |-----------------|-----------------|-----------------|-----------------|
---  |                                                   enable_input0 = [0] |  0
+--  |                                             fifo_used_words stream 0  |  0
 --  |-----------------------------------------------------------------------|
---  |                                                   enable_input1 = [0] |  1
+--  |                      wr_fifo_full = [1] rd_fifo_empty = [0] stream 0  |  1
 --  |-----------------------------------------------------------------------|
---  |                                                   enable_input2 = [0] |  2
+--  |                                         max_fifo_used_words stream 0  |  2
+--  |-----------------------------------------------------------------------|
+--  |                                             fifo_used_words stream 1  |  3
+--  |-----------------------------------------------------------------------|
+--  |                      wr_fifo_full = [1] rd_fifo_empty = [0] stream 1  |  4
+--  |-----------------------------------------------------------------------|
+--  |                                         max_fifo_used_words stream 1  |  5
 --  |-----------------------------------------------------------------------|
 --                                      |   
 --                                      |
 --  |-----------------------------------------------------------------------|
---  |                                                  enable_input.. = [0] |  g_nof_inputs-1
+--  |                                             fifo_used_words stream x  |  
+--  |-----------------------------------------------------------------------|
+--  |                      wr_fifo_full = [1] rd_fifo_empty = [0] stream x  |  
+--  |-----------------------------------------------------------------------|
+--  |                                         max_fifo_used_words stream x  |  
 --  |-----------------------------------------------------------------------|
 
 
@@ -70,8 +80,9 @@ END dp_fifo_fill_reg;
 
 
 ARCHITECTURE str OF dp_fifo_fill_reg IS
-
-  CONSTANT c_nof_regs_per_stream : NATURAL := 2; 
+  
+  CONSTANT c_reg_max_used_words_offset : NATURAL := 2; 
+  CONSTANT c_nof_regs_per_stream       : NATURAL := 3; 
   
   -- Define the actual size of the MM slave register
   CONSTANT c_mm_reg : t_c_mem := (latency  => 1,
@@ -84,12 +95,14 @@ ARCHITECTURE str OF dp_fifo_fill_reg IS
   SIGNAL in_arr_reg  : STD_LOGIC_VECTOR(g_nof_streams*c_nof_regs_per_stream*c_word_w-1 DOWNTO 0) := (OTHERS=>'0');
   SIGNAL reg_wr_arr  : STD_LOGIC_VECTOR(g_nof_streams*c_nof_regs_per_stream-1          DOWNTO 0) := (OTHERS=>'0');  
   SIGNAL reg_rd_arr  : STD_LOGIC_VECTOR(g_nof_streams*c_nof_regs_per_stream-1          DOWNTO 0) := (OTHERS=>'0');  
+  SIGNAL peak_used_w : STD_LOGIC_VECTOR(g_nof_streams*c_word_w-1                       DOWNTO 0) := (OTHERS=>'0');
 
 BEGIN
 
   gen_in_arr_reg : FOR I IN 0 TO g_nof_streams-1 GENERATE
-    in_arr_reg((2*I+1)*c_word_w-1 DOWNTO 2*I*c_word_w)     <= used_w((I+1)*c_word_w-1 DOWNTO I*c_word_w);
-    in_arr_reg((2*I+1)*c_word_w+1 DOWNTO (2*I+1)*c_word_w) <= wr_ful(I) & rd_emp(I);
+    in_arr_reg((c_nof_regs_per_stream*I+1)*c_word_w-1  DOWNTO  c_nof_regs_per_stream*I   *c_word_w) <= used_w((I+1)*c_word_w-1 DOWNTO I*c_word_w);
+    in_arr_reg((c_nof_regs_per_stream*I+2)*c_word_w-31 DOWNTO (c_nof_regs_per_stream*I+1)*c_word_w) <= wr_ful(I) & rd_emp(I);                     
+    in_arr_reg((c_nof_regs_per_stream*I+3)*c_word_w-1  DOWNTO (c_nof_regs_per_stream*I+2)*c_word_w) <= peak_used_w((I+1)*c_word_w-1 DOWNTO I*c_word_w);
   END GENERATE;
 
   u_reg : ENTITY common_lib.common_reg_r_w_dc
@@ -120,5 +133,21 @@ BEGIN
     out_new     => OPEN
   );
   
+  gen_peak_meters : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    u_peak_meter : ENTITY common_lib.common_peak
+    GENERIC MAP(
+      g_dat_w => c_word_w
+    )
+    PORT MAP (
+      rst       => st_rst,
+      clk       => st_clk,
+      in_dat    => used_w((I+1)*c_word_w-1 DOWNTO I*c_word_w),
+      in_val    => '1',
+      in_clear  => reg_rd_arr(I*c_nof_regs_per_stream + c_reg_max_used_words_offset),
+      out_dat   => peak_used_w((I+1)*c_word_w-1 DOWNTO I*c_word_w),
+      out_val   => OPEN
+    );
+  END GENERATE;
+  
 END str;