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Commit 2e17e4dc authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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unb2b_jesd: design initial commit

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Quick steps to compile and use design [unb2b_jesd] in RadionHDL
------------------------------------------------------------------
On uni-boards 26287-001..26287-005 (unb2b) the used FPGA is '10AX115U2F45E1SG'
-> In case of a new installation, the IP's have to be generated for Arria10.
In the: $RADIOHDL/libraries/technology/ip_arria10
directory; run the bash script: ./generate-all-ip.sh
-> For compilation it might be necessary to check the .vhd file:
$RADIOHDL/libraries/technology/technology_select_pkg.vhd
-> Make sure you have set up the RadioHDL/trunk/tools/quartus/set_quartus script correctly to use quartus 17 for unb2b.
-> Make sure you use the modified avs2_eth_coe_hw.tcl (see attachment of this e-mail), this file is placed in RadioHDL/trunk/libraries/io/eth/src/vhdl.
1. Start with the Oneclick Commands:
python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2b
python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2b
# 2. Generate MMM for QSYS:
# run_qsys unb2b unb2b_jesd
3. -> From here either continue to Modelsim (simulation) or Quartus (synthesis)
Simulation
----------
Modelsim instructions:
# in bash do:
rm $UNB/Software/python/sim/* # (optional)
run_modelsim unb2b
# in Modelsim do:
lp unb2b_jesd
mk all
# now double click on testbench file
as 10
run 500us
# while the simulation runs... in another bash session do:
cd unb2b_jesd/tb/python
python tc_unb2b_jesd.py --sim --unb 0 --fn 3 --seq INFO,PPSH,SENSORS
# (sensor results only show up after 1000us of simulation runtime)
# to end simulation in Modelsim do:
quit -sim
Synthesis
---------
# Quartus instructions:
# run_qcomp unb2 unb2b_jesd
# scripts are not yet working for quartus 17.0.2, this is the workaround.
- "run_quartus unb2b &"
- Open the unb2b_minumal quartus project from the build directory.
- Open the qsys_unb2b_jesd.qsys file from the build directory.
- Generate the HDL files for the qsys using the GUI.
- "cd $RADIOHDL/build/unb2b/quartus/unb2b_jesd"
- "cp qsys_unb2b_jesd/qsys_unb2b_jesd* ."
- "run_app unb2b unb2b_jesd use=gen2"
- In Quartus, click the play button to compile the design.
if project ip's are missing problably /home/[user name]/.altera.quartus/ip/17.0.2/ is missing.
(just make a copy of the previous one and rename it)
4. Load firmware
----------------
Using JTAG: Start the Quartus GUI and open: tools->programmer.
Then click auto-detect;
Use 'change file' to select the correct .sof file for each FPGA
Select the FPGA(s) which has to be programmed
Click 'start'
Using EPCS: See step 6 below.
5. Testing on hardware
----------------------
Assuming the firmware is loaded and running already in the FPGA, the firmware can be tested from the connected
LCU computer.
# (assume that the Uniboard is --unb 1)
# To read out the design_name, ppsh and sensors; do:
python tc_unb2_jesd.py --unb 1 --fn 0:3 --seq REGMAP,INFO,PPSH,SENSORS -v5
6. Programming the EPCS flash.
------------------------------
On an empty new board the factory image must be loaded using the programmer and a yic file.
when the EPCS module works (factory image is loaded in flash) an RBF file can be generated to program the flash,
then the .sof file file can be converted to .rbf with the 'run_rbf' script.
But for now the only way to program the EPCS flash is via JTAG.
Firstly a JIC file has to be generated from the SOF file.
In Quartus GUI; open current project; File -> Convert Programming Files.
Then setup:
- Output programming file: JIC
- Configuration device: EPCQ-L1024
- Mode: Active Serial x4
- Flash Loader: Add/Select Device Arria10 / 10AX115U2
- SOF Data: add file (the generated .sof file)
- click the .sof file; Set property 'Compression' to ON
- Press 'Generate'
- Press "Done"
In Quartus GUI:
Setup Device (if needed):
- click in menu: 'Assignments' -> 'Device'
- Name: 10AX115U2F45E1SG
- click 'Device and Pin Options' button.
- Configuration scheme: Active Serial x4
- check Use Configuration device: EPCQL1024.
- Configuration device I/O voltage: 1.8V
- check Generate compressed bitstreams.
- Active clock source: 12.5 MHz Internal Oscillator.
Then program the .JIC file (output_file.jic) to EPCS flash:
- Make sure that the JTAG (on server connected to board) runs at 16MHz:
/home/software/software/Altera/17.0/quartus/bin/jtagconfig USB-BlasterII JtagClock 16M
- open tools->programmer
- make sure the 4 fpga icons have the device 10AX115U2F45
- right-click each fpga icon and attach flash device EPCQ-L1024
- right-click each EPCQ-L1024 and change file from <none> to output_file.jic
- check each Program/Configure radiobutton for the EPCQ-L1024, the right 'sfl' file is auto selected and checked.
- click start and wait for 'Successful'
- restart the board by toggling the button on the front (only needed the first time)
hdl_lib_name = unb2b_jesd
hdl_library_clause_name = unb2b_jesd_lib
hdl_lib_uses_synth = common technology mm unb2b_board diag dp
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
src/vhdl/qsys_unb2b_jesd_pkg.vhd
src/vhdl/mmm_unb2b_jesd.vhd
src/vhdl/unb2b_jesd.vhd
test_bench_files =
tb/vhdl/tb_unb2b_jesd.vhd
[modelsim_project_file]
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
quartus .
quartus_qsf_files =
$RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_files =
quartus/unb2b_jesd.sdc
quartus_tcl_files =
quartus/unb2_jesd_pins.tcl
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2b/quartus/unb2b_jesd/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
Source diff could not be displayed: it is too large. Options to address this: view the blob.
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>Intel Corporation</spirit:vendor>
<spirit:library>altjesd_ss_RX_frame_reset</spirit:library>
<spirit:name>altjesd_ss_RX_frame_reset</spirit:name>
<spirit:version>18.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>clk</spirit:name>
<spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
<spirit:slave></spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>clk</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>clockRate</spirit:name>
<spirit:displayName>Clock rate</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>externallyDriven</spirit:name>
<spirit:displayName>Externally driven</spirit:displayName>
<spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ptfSchematicName</spirit:name>
<spirit:displayName>PTF schematic name</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>in_reset</spirit:name>
<spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
<spirit:slave></spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>reset_n</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>in_reset_n</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
<spirit:displayName>Associated clock</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>synchronousEdges</spirit:name>
<spirit:displayName>Synchronous edges</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>out_reset</spirit:name>
<spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
<spirit:master></spirit:master>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>reset_n</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>out_reset_n</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
<spirit:displayName>Associated clock</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>associatedDirectReset</spirit:name>
<spirit:displayName>Associated direct reset</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="associatedDirectReset">in_reset</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>associatedResetSinks</spirit:name>
<spirit:displayName>Associated reset sinks</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="associatedResetSinks">in_reset</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>synchronousEdges</spirit:name>
<spirit:displayName>Synchronous edges</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>QUARTUS_SYNTH</spirit:name>
<spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
<spirit:modelName>altera_reset_bridge</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>QUARTUS_SYNTH</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>in_reset_n</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>out_reset_n</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>Intel Corporation</spirit:vendor>
<spirit:library>altjesd_ss_RX_frame_reset</spirit:library>
<spirit:name>altera_reset_bridge</spirit:name>
<spirit:version>18.0</spirit:version>
</altera:entity_info>
<altera:altera_module_parameters>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ACTIVE_LOW_RESET</spirit:name>
<spirit:displayName>Active low reset</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="ACTIVE_LOW_RESET">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>SYNCHRONOUS_EDGES</spirit:name>
<spirit:displayName>Synchronous edges</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="SYNCHRONOUS_EDGES">deassert</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_RESET_OUTPUTS</spirit:name>
<spirit:displayName>Number of reset outputs</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="NUM_RESET_OUTPUTS">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>USE_RESET_REQUEST</spirit:name>
<spirit:displayName>Use reset request signal</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="USE_RESET_REQUEST">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>SYNC_RESET</spirit:name>
<spirit:displayName>Use synchronous resets</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="SYNC_RESET">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>AUTO_CLK_CLOCK_RATE</spirit:name>
<spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="AUTO_CLK_CLOCK_RATE">100000000</spirit:value>
</spirit:parameter>
</spirit:parameters>
</altera:altera_module_parameters>
<altera:altera_system_parameters>
<spirit:parameters>
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
<spirit:displayName>Device family</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceSpeedGrade</spirit:name>
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>generationId</spirit:name>
<spirit:displayName>Generation Id</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="bonusData">bonusData
{
}
</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>hideFromIPCatalog</spirit:name>
<spirit:displayName>Hide from IP Catalog</spirit:displayName>
<spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>lockedInterfaceDefinition</spirit:name>
<spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>in_reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>out_reset</name>
<type>reset</type>
<isStart>true</isStart>
<ports>
<port>
<name>out_reset_n</name>
<role>reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedDirectReset</key>
<value>in_reset</value>
</entry>
<entry>
<key>associatedResetSinks</key>
<value>in_reset</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>systemInfos</spirit:name>
<spirit:displayName>systemInfos</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos>
<entry>
<key>clk</key>
<value>
<connectionPointName>clk</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>100000000</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfosDefinition>]]></spirit:value>
</spirit:parameter>
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
<altera:interface_mapping altera:name="clk" altera:internal="altjesd_ss_RX_frame_reset.clk" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="in_reset" altera:internal="altjesd_ss_RX_frame_reset.in_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="in_reset_n" altera:internal="in_reset_n"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="out_reset" altera:internal="altjesd_ss_RX_frame_reset.out_reset" altera:type="reset" altera:dir="start">
<altera:port_mapping altera:name="out_reset_n" altera:internal="out_reset_n"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
<altera:altera_has_warnings>false</altera:altera_has_warnings>
<altera:altera_has_errors>false</altera:altera_has_errors>
</spirit:vendorExtensions>
</spirit:component>
\ No newline at end of file
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>Intel Corporation</spirit:vendor>
<spirit:library>altjesd_ss_RX_link_reset</spirit:library>
<spirit:name>altjesd_ss_RX_link_reset</spirit:name>
<spirit:version>18.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>clk</spirit:name>
<spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
<spirit:slave></spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>clk</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>clockRate</spirit:name>
<spirit:displayName>Clock rate</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>externallyDriven</spirit:name>
<spirit:displayName>Externally driven</spirit:displayName>
<spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ptfSchematicName</spirit:name>
<spirit:displayName>PTF schematic name</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>in_reset</spirit:name>
<spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
<spirit:slave></spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>reset_n</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>in_reset_n</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
<spirit:displayName>Associated clock</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>synchronousEdges</spirit:name>
<spirit:displayName>Synchronous edges</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>out_reset</spirit:name>
<spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
<spirit:master></spirit:master>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>reset_n</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>out_reset_n</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
<spirit:displayName>Associated clock</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>associatedDirectReset</spirit:name>
<spirit:displayName>Associated direct reset</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="associatedDirectReset">in_reset</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>associatedResetSinks</spirit:name>
<spirit:displayName>Associated reset sinks</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="associatedResetSinks">in_reset</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>synchronousEdges</spirit:name>
<spirit:displayName>Synchronous edges</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>QUARTUS_SYNTH</spirit:name>
<spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
<spirit:modelName>altera_reset_bridge</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>QUARTUS_SYNTH</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>in_reset_n</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>out_reset_n</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>Intel Corporation</spirit:vendor>
<spirit:library>altjesd_ss_RX_link_reset</spirit:library>
<spirit:name>altera_reset_bridge</spirit:name>
<spirit:version>18.0</spirit:version>
</altera:entity_info>
<altera:altera_module_parameters>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ACTIVE_LOW_RESET</spirit:name>
<spirit:displayName>Active low reset</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="ACTIVE_LOW_RESET">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>SYNCHRONOUS_EDGES</spirit:name>
<spirit:displayName>Synchronous edges</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="SYNCHRONOUS_EDGES">deassert</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_RESET_OUTPUTS</spirit:name>
<spirit:displayName>Number of reset outputs</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="NUM_RESET_OUTPUTS">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>USE_RESET_REQUEST</spirit:name>
<spirit:displayName>Use reset request signal</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="USE_RESET_REQUEST">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>SYNC_RESET</spirit:name>
<spirit:displayName>Use synchronous resets</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="SYNC_RESET">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>AUTO_CLK_CLOCK_RATE</spirit:name>
<spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="AUTO_CLK_CLOCK_RATE">100000000</spirit:value>
</spirit:parameter>
</spirit:parameters>
</altera:altera_module_parameters>
<altera:altera_system_parameters>
<spirit:parameters>
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
<spirit:displayName>Device family</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceSpeedGrade</spirit:name>
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>generationId</spirit:name>
<spirit:displayName>Generation Id</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="bonusData">bonusData
{
}
</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>hideFromIPCatalog</spirit:name>
<spirit:displayName>Hide from IP Catalog</spirit:displayName>
<spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>lockedInterfaceDefinition</spirit:name>
<spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>in_reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>out_reset</name>
<type>reset</type>
<isStart>true</isStart>
<ports>
<port>
<name>out_reset_n</name>
<role>reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedDirectReset</key>
<value>in_reset</value>
</entry>
<entry>
<key>associatedResetSinks</key>
<value>in_reset</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>systemInfos</spirit:name>
<spirit:displayName>systemInfos</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos>
<entry>
<key>clk</key>
<value>
<connectionPointName>clk</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>100000000</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfosDefinition>]]></spirit:value>
</spirit:parameter>
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
<altera:interface_mapping altera:name="clk" altera:internal="altjesd_ss_RX_link_reset.clk" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="in_reset" altera:internal="altjesd_ss_RX_link_reset.in_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="in_reset_n" altera:internal="in_reset_n"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="out_reset" altera:internal="altjesd_ss_RX_link_reset.out_reset" altera:type="reset" altera:dir="start">
<altera:port_mapping altera:name="out_reset_n" altera:internal="out_reset_n"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
<altera:altera_has_warnings>false</altera:altera_has_warnings>
<altera:altera_has_errors>false</altera:altera_has_errors>
</spirit:vendorExtensions>
</spirit:component>
\ No newline at end of file
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