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Commit 2e024bd1 authored by Reinier van der Walle's avatar Reinier van der Walle
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Merge branch 'HPR-122' into 'master'

corrected minor faults

Closes HPR-122

See merge request desp/hdl!333
parents bb8729da 08b0b0f7
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1 merge request!333corrected minor faults
Pipeline #51196 passed
...@@ -227,6 +227,7 @@ ARCHITECTURE rtl OF dp_repack_in IS ...@@ -227,6 +227,7 @@ ARCHITECTURE rtl OF dp_repack_in IS
-- Debug signals -- Debug signals
SIGNAL snk_in_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0); SIGNAL snk_in_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL i_src_out : t_dp_sosi; SIGNAL i_src_out : t_dp_sosi;
SIGNAL i_src_out_data : STD_LOGIC_VECTOR(c_in_buf_dat_w-1 DOWNTO 0);
SIGNAL dbg_g_in_dat_w : NATURAL := g_in_dat_w; SIGNAL dbg_g_in_dat_w : NATURAL := g_in_dat_w;
SIGNAL dbg_in_nof_words : NATURAL := g_in_nof_words; SIGNAL dbg_in_nof_words : NATURAL := g_in_nof_words;
...@@ -238,10 +239,12 @@ BEGIN ...@@ -238,10 +239,12 @@ BEGIN
snk_in_data <= snk_in.data(g_in_dat_w-1 DOWNTO 0); snk_in_data <= snk_in.data(g_in_dat_w-1 DOWNTO 0);
src_out <= i_src_out; src_out <= i_src_out;
src_out_data <= i_src_out_data;
gen_bypass : IF g_bypass=TRUE GENERATE gen_bypass : IF g_bypass=TRUE GENERATE
snk_out <= src_in; snk_out <= src_in;
i_src_out <= snk_in; i_src_out <= snk_in;
i_src_out_data <= RESIZE_UVEC(snk_in.data, c_in_buf_dat_w);
END GENERATE; END GENERATE;
no_bypass : IF g_bypass=FALSE GENERATE no_bypass : IF g_bypass=FALSE GENERATE
...@@ -367,7 +370,7 @@ BEGIN ...@@ -367,7 +370,7 @@ BEGIN
-------------------------------------------------------------------------- --------------------------------------------------------------------------
-- Wired output -- Wired output
i_src_out <= r.src_out; i_src_out <= r.src_out;
src_out_data <= r.src_out_data; i_src_out_data <= r.src_out_data;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
-- Flow control -- Flow control
...@@ -444,7 +447,6 @@ ARCHITECTURE rtl OF dp_repack_out IS ...@@ -444,7 +447,6 @@ ARCHITECTURE rtl OF dp_repack_out IS
SIGNAL nxt_r : t_reg; SIGNAL nxt_r : t_reg;
-- Debug signals -- Debug signals
SIGNAL i_src_out_data : STD_LOGIC_VECTOR(g_in_buf_dat_w-1 DOWNTO 0);
SIGNAL i_src_out : t_dp_sosi; SIGNAL i_src_out : t_dp_sosi;
SIGNAL src_out_data : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); SIGNAL src_out_data : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
...@@ -459,7 +461,7 @@ ARCHITECTURE rtl OF dp_repack_out IS ...@@ -459,7 +461,7 @@ ARCHITECTURE rtl OF dp_repack_out IS
BEGIN BEGIN
src_out <= i_src_out; src_out <= i_src_out;
src_out_data <= i_src_out_data(g_out_dat_w-1 DOWNTO 0); src_out_data <= i_src_out.data(g_out_dat_w-1 DOWNTO 0);
gen_bypass : IF g_bypass=TRUE GENERATE gen_bypass : IF g_bypass=TRUE GENERATE
snk_out <= src_in; snk_out <= src_in;
...@@ -468,11 +470,11 @@ BEGIN ...@@ -468,11 +470,11 @@ BEGIN
BEGIN BEGIN
i_src_out <= snk_in; i_src_out <= snk_in;
IF c_snk_in_dat_lo>0 THEN IF c_snk_in_dat_lo>0 THEN
i_src_out_data <= SHIFT_UVEC(snk_in_data, c_snk_in_dat_lo); i_src_out.data <= SHIFT_UVEC(RESIZE_DP_DATA(snk_in_data), c_snk_in_dat_lo);
i_src_out.empty <= INCR_UVEC( snk_in.empty, -c_snk_in_dat_lo); i_src_out.empty <= INCR_UVEC( snk_in.empty, -c_snk_in_dat_lo);
END IF; END IF;
IF c_out_buf_dat_lo>0 THEN IF c_out_buf_dat_lo>0 THEN
i_src_out_data <= SHIFT_UVEC(snk_in_data, -c_out_buf_dat_lo); i_src_out.data <= SHIFT_UVEC(RESIZE_DP_DATA(snk_in_data), -c_out_buf_dat_lo);
i_src_out.empty <= INCR_UVEC( snk_in.empty, c_out_buf_dat_lo); i_src_out.empty <= INCR_UVEC( snk_in.empty, c_out_buf_dat_lo);
END IF; END IF;
END PROCESS; END PROCESS;
......
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