corrected minor faults

libraries/base/dp/src/vhdl/dp_repack_data.vhd

@@ -227,6 +227,7 @@ ARCHITECTURE rtl OF dp_repack_in IS
   -- Debug signals
   SIGNAL snk_in_data        : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
   SIGNAL i_src_out          : t_dp_sosi;
+  SIGNAL i_src_out_data     : STD_LOGIC_VECTOR(c_in_buf_dat_w-1 DOWNTO 0);
 
   SIGNAL dbg_g_in_dat_w   : NATURAL := g_in_dat_w;
   SIGNAL dbg_in_nof_words : NATURAL := g_in_nof_words;
@@ -238,10 +239,12 @@ BEGIN
   snk_in_data <= snk_in.data(g_in_dat_w-1 DOWNTO 0);
   
   src_out      <= i_src_out;
+  src_out_data <= i_src_out_data;
   
   gen_bypass : IF g_bypass=TRUE GENERATE
-    snk_out   <= src_in;
-    i_src_out <= snk_in;
+    snk_out        <= src_in;
+    i_src_out      <= snk_in;
+    i_src_out_data <= RESIZE_UVEC(snk_in.data, c_in_buf_dat_w);
   END GENERATE;
   
   no_bypass : IF g_bypass=FALSE GENERATE
@@ -367,7 +370,7 @@ BEGIN
     --------------------------------------------------------------------------
     -- Wired output
     i_src_out <= r.src_out;
-    src_out_data <= r.src_out_data;
+    i_src_out_data <= r.src_out_data;
     --------------------------------------------------------------------------
     -- Flow control
   
@@ -444,7 +447,6 @@ ARCHITECTURE rtl OF dp_repack_out IS
   SIGNAL nxt_r     : t_reg;
 
   -- Debug signals
-  SIGNAL i_src_out_data     : STD_LOGIC_VECTOR(g_in_buf_dat_w-1 DOWNTO 0);
   SIGNAL i_src_out          : t_dp_sosi;
   SIGNAL src_out_data       : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
 
@@ -459,7 +461,7 @@ ARCHITECTURE rtl OF dp_repack_out IS
 BEGIN
 
   src_out      <= i_src_out;
-  src_out_data <= i_src_out_data(g_out_dat_w-1 DOWNTO 0);
+  src_out_data <= i_src_out.data(g_out_dat_w-1 DOWNTO 0);
   
   gen_bypass : IF g_bypass=TRUE GENERATE
     snk_out <= src_in;
@@ -468,11 +470,11 @@ BEGIN
     BEGIN
       i_src_out <= snk_in;
       IF c_snk_in_dat_lo>0 THEN
-        i_src_out_data  <= SHIFT_UVEC(snk_in_data,   c_snk_in_dat_lo);
+        i_src_out.data  <= SHIFT_UVEC(RESIZE_DP_DATA(snk_in_data), c_snk_in_dat_lo);
         i_src_out.empty <= INCR_UVEC( snk_in.empty, -c_snk_in_dat_lo);
       END IF;
       IF c_out_buf_dat_lo>0 THEN
-        i_src_out_data  <= SHIFT_UVEC(snk_in_data, -c_out_buf_dat_lo);
+        i_src_out.data  <= SHIFT_UVEC(RESIZE_DP_DATA(snk_in_data), -c_out_buf_dat_lo);
         i_src_out.empty <= INCR_UVEC( snk_in.empty, c_out_buf_dat_lo);
       END IF;
     END PROCESS;