Added some more notes.

doc/erko_hdl_design_article.txt

@@ -43,3 +43,33 @@ $RADIOHDL_WORK/applications/lofar2/doc/prestudy/
 Ref:
  $RADIOHDL/tools/oneclick/doc/desp_firmware_dag_erko.txt
  $RADIOHDL/tools/oneclick/doc/desp_firmware_overview.txt
+
+
+HDL coding: Useful documents about with fundamental knowledge for digital logic in FPGAs and ASICs:
+  - Memory mapped RAM and registers and clock domain crossing. Thanks to these standard components we
+    can run the mm_clk at another rate than the dp_clk:
+    https://svn.astron.nl/UniBoard_FP7/RadioHDL/trunk/libraries/base/common/doc/ASTRON_RP_415_common_mem.pdf
+    https://svn.astron.nl/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/async_logic/doc/async_logic.pdf
+    About meta stability and asynchronous logic. This doc cointains solutions for:
+    . synchronizing a reset to a clock domain,
+    . transfering a level signal between clock domains
+    . transfering a pulse signal between clock domains
+      It als contains a study that I did to understand how the control of a dual clock FIFO works. Typically
+      we use an IP component as FIFO, but I think the async_fifo RTL code would also work on HW, it does
+      work in simulation.
+  - RTL combinatorial D --> D, rising_edge D --> Q
+    . complicates functional thinking because mixes combinatorial (valid now) and clocked (valid one
+      cylce later)
+    . latency of D --> Q complicates backpressure (RL = 1)
+    . introduces non-functional pipeline, mixes state reg and pipeline reg
+    Gaisler structures this RTL D --> Q coding style, but does not solve these complications
+    Gaisler uses variables, but does not structure the use of variables
+
+Ik zie twee niveaus:
+1) Als de FPGA synthese & timing aangeeft dat het goed is, dan is de FPGA logic foutloos
+  (dwz what you code is what you get).
+2) Als we goed ontwerpen, implementeren en testen, zorgen dat FIFOs niet overstromen, en zorgen
+   dat de packets die binnenkomen van buiten de FPGA correct zijn (bijv. mbv CRC ok) dan is de
+   block processing foutloos (dwz what you want is what you get). Dan kunnen we er intern steeds
+   van uitgaan dat de blokken data correct zijn en hoeven we dus intern geen checks meer te doen.
+