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Commit 2def004f authored by Eric Kooistra's avatar Eric Kooistra
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Use g_use_tech_jesd204b_v2 as generic instead of internal constant, to allow...

Use g_use_tech_jesd204b_v2 as generic instead of internal constant, to allow different selection in designs.
parent cc1b0fa2
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1 merge request!381rx_clk -> dp_clk FIFO in JESD204b component.
Pipeline #71485 passed
...@@ -38,6 +38,9 @@ use work.sdp_pkg.all; ...@@ -38,6 +38,9 @@ use work.sdp_pkg.all;
entity node_sdp_adc_input_and_timing is entity node_sdp_adc_input_and_timing is
generic ( generic (
g_no_jesd : boolean := false; g_no_jesd : boolean := false;
-- Use tech_jesd204b with tech_jesd204b and FIFO in ait, or
-- use tech_jesd204b_v2 with FIFO in tech_jesd204b_v2
g_use_tech_jesd204b_v2 : boolean := false;
g_buf_nof_data : natural := c_sdp_V_si_db; g_buf_nof_data : natural := c_sdp_V_si_db;
g_bsn_nof_clk_per_sync : natural := c_sdp_N_clk_per_sync; -- Default 200M, overide for short simulation g_bsn_nof_clk_per_sync : natural := c_sdp_N_clk_per_sync; -- Default 200M, overide for short simulation
g_sim : boolean := false g_sim : boolean := false
...@@ -110,10 +113,6 @@ entity node_sdp_adc_input_and_timing is ...@@ -110,10 +113,6 @@ entity node_sdp_adc_input_and_timing is
end node_sdp_adc_input_and_timing; end node_sdp_adc_input_and_timing;
architecture str of node_sdp_adc_input_and_timing is architecture str of node_sdp_adc_input_and_timing is
-- Use tech_jesd204b with tech_jesd204b and FIFO in ait, or
-- use tech_jesd204b_v2 with FIFO in tech_jesd204b_v2
constant c_use_tech_jesd204b_v2 : boolean := false;
-- Waveform Generator -- Waveform Generator
constant c_wg_buf_directory : string := "data/"; constant c_wg_buf_directory : string := "data/";
constant c_wg_buf_dat_w : natural := 18; -- default value of WG that fits 14 bits of ADC data constant c_wg_buf_dat_w : natural := 18; -- default value of WG that fits 14 bits of ADC data
...@@ -215,7 +214,7 @@ begin ...@@ -215,7 +214,7 @@ begin
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- JESD204B IP (ADC Handler) -- JESD204B IP (ADC Handler)
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
gen_jesd204b_v1 : if c_use_tech_jesd204b_v2 = false generate gen_jesd204b_v1 : if g_use_tech_jesd204b_v2 = false generate
u_jesd204b_v1 : entity tech_jesd204b_lib.tech_jesd204b u_jesd204b_v1 : entity tech_jesd204b_lib.tech_jesd204b
generic map( generic map(
g_sim => false, -- do not use g_sim, because JESD204B IP does support mm_clk in sim g_sim => false, -- do not use g_sim, because JESD204B IP does support mm_clk in sim
...@@ -248,7 +247,7 @@ begin ...@@ -248,7 +247,7 @@ begin
); );
end generate; end generate;
gen_jesd204b_v2 : if c_use_tech_jesd204b_v2 = true generate gen_jesd204b_v2 : if g_use_tech_jesd204b_v2 = true generate
u_jesd204b_v2: entity tech_jesd204b_lib.tech_jesd204b_v2 u_jesd204b_v2: entity tech_jesd204b_lib.tech_jesd204b_v2
generic map( generic map(
g_sim => false, -- do not use g_sim, because JESD204B IP does support mm_clk in sim g_sim => false, -- do not use g_sim, because JESD204B IP does support mm_clk in sim
...@@ -283,7 +282,7 @@ begin ...@@ -283,7 +282,7 @@ begin
end generate; -- gen_jesd end generate; -- gen_jesd
-- Wire rx_clk from tech_jesd204b to AIT -- Wire rx_clk from tech_jesd204b to AIT
gen_rx_ait : if g_no_jesd = false and c_use_tech_jesd204b_v2 = false generate gen_rx_ait : if g_no_jesd = false and g_use_tech_jesd204b_v2 = false generate
u_rx_ait : entity work.sdp_adc_input_and_timing u_rx_ait : entity work.sdp_adc_input_and_timing
generic map ( generic map (
g_no_rx => g_no_jesd, -- when false use Rx and WG, else only use WG g_no_rx => g_no_jesd, -- when false use Rx and WG, else only use WG
...@@ -401,7 +400,7 @@ begin ...@@ -401,7 +400,7 @@ begin
end generate; -- gen_rx_ait end generate; -- gen_rx_ait
-- Wire dp_clk to AIT when jesd is not used or when jesd IP tech_jesd204b_v2 is used -- Wire dp_clk to AIT when jesd is not used or when jesd IP tech_jesd204b_v2 is used
gen_dp_ait : if g_no_jesd = true or (g_no_jesd = false and c_use_tech_jesd204b_v2 = true) generate gen_dp_ait : if g_no_jesd = true or (g_no_jesd = false and g_use_tech_jesd204b_v2 = true) generate
u_dp_ait : entity work.sdp_adc_input_and_timing u_dp_ait : entity work.sdp_adc_input_and_timing
generic map ( generic map (
g_no_rx => g_no_jesd, -- when false use Rx and WG, else only use WG g_no_rx => g_no_jesd, -- when false use Rx and WG, else only use WG
......
...@@ -63,6 +63,9 @@ entity sdp_station is ...@@ -63,6 +63,9 @@ entity sdp_station is
g_scope_selected_subband : natural := 0; g_scope_selected_subband : natural := 0;
-- Use no default, to force instance to set it -- Use no default, to force instance to set it
g_no_jesd : boolean; g_no_jesd : boolean;
-- Use tech_jesd204b with tech_jesd204b and FIFO in ait, or
-- use tech_jesd204b_v2 with FIFO in tech_jesd204b_v2
g_use_tech_jesd204b_v2 : boolean := true; --false;
g_use_fsub : boolean; g_use_fsub : boolean;
g_use_oversample : boolean; g_use_oversample : boolean;
g_use_xsub : boolean; g_use_xsub : boolean;
...@@ -671,6 +674,7 @@ begin ...@@ -671,6 +674,7 @@ begin
generic map( generic map(
g_sim => g_sim, g_sim => g_sim,
g_no_jesd => g_no_jesd, g_no_jesd => g_no_jesd,
g_use_tech_jesd204b_v2 => g_use_tech_jesd204b_v2,
g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync
) )
port map( port map(
......
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