Removed sum_sop, only need to use sum_sync. Added purpose and description description.

libraries/io/aduh/src/vhdl/aduh_mean_sum.vhd

@@ -19,6 +19,14 @@
 --
 -------------------------------------------------------------------------------
 
+-- Purpose : Calculate the signed 'voltage' sum of input symbols during a sync
+--           interval
+-- Description :
+--   The in_data can have g_nof_symbols_per_data >= 1 per in_data word.
+--   The sync interval starts with the in_data that is valid at the in_sync.
+--   The output 'voltage' sum of the previous sync interval is valid at the
+--   sum_sync and held until the next sum_sync.
+
 LIBRARY IEEE, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
@@ -43,8 +51,7 @@ ENTITY aduh_mean_sum IS
     
     -- Accumulation outputs
     sum         : OUT STD_LOGIC_VECTOR(g_sum_w-1 DOWNTO 0);
-    sum_sync    : OUT STD_LOGIC;                    -- after sync there is a new sum
-    sum_sop     : OUT STD_LOGIC                     -- at    sop  there is a new sum
+    sum_sync    : OUT STD_LOGIC   -- at sum_sync there is a new sum
   );
 END aduh_mean_sum;
 
@@ -59,41 +66,29 @@ ARCHITECTURE rtl OF aduh_mean_sum IS
   TYPE t_symbol_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_symbol_w-1 DOWNTO 0);
   TYPE t_acc_arr    IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(   c_acc_w-1 DOWNTO 0);
   
-  SIGNAL acc_load     : STD_LOGIC;
-  SIGNAL nxt_acc_load : STD_LOGIC;
-  SIGNAL acc_load_p   : STD_LOGIC;
-
+  SIGNAL in_sync_p    : STD_LOGIC;  
   SIGNAL symbol_arr   : t_symbol_arr(0 TO g_nof_symbols_per_data-1);
   SIGNAL acc_arr      : t_acc_arr(   0 TO g_nof_symbols_per_data-1);
   SIGNAL acc_vec      : STD_LOGIC_VECTOR(g_nof_symbols_per_data*c_acc_w-1 DOWNTO 0);
-  
   SIGNAL acc_sum      : STD_LOGIC_VECTOR(c_acc_sum_w-1 DOWNTO 0);
-
   SIGNAL i_sum        : STD_LOGIC_VECTOR(g_sum_w-1 DOWNTO 0);
   SIGNAL nxt_sum      : STD_LOGIC_VECTOR(g_sum_w-1 DOWNTO 0);
-
-  SIGNAL i_sum_sync   : STD_LOGIC;
+  SIGNAL nxt_sum_sync : STD_LOGIC;
   
 BEGIN
 
-  sum      <= i_sum;
-  sum_sync <= i_sum_sync;
+  sum <= i_sum;
   
   regs : PROCESS(rst,clk)
   BEGIN
     IF rst='1' THEN
-      acc_load <= '0';
       i_sum    <= (OTHERS => '0');
-      sum_sop  <= '0';
+      sum_sync <= '0';
     ELSIF rising_edge(clk) THEN
-      acc_load <= nxt_acc_load;
       i_sum    <= nxt_sum;
-      sum_sop  <= i_sum_sync;
+      sum_sync <= nxt_sum_sync;
     END IF;
   END PROCESS;
-  
-  -- Reload the accumlators with 0 or with the valid sample after the sync
-  nxt_acc_load <= in_sync;
 
   -- Accumulate per symbol stream in the in_data 
   gen_acc : FOR I IN 0 TO g_nof_symbols_per_data-1 GENERATE
@@ -106,7 +101,7 @@ BEGIN
     PORT MAP(
       rst     => rst,
       clk     => clk,
-      sload   => acc_load,
+      sload   => in_sync,  -- Reload the accumlators with 0 at the sync or with the valid sample after the sync
       in_val  => in_val,
       in_dat  => symbol_arr(I),
       out_dat => acc_arr(I)
@@ -117,10 +112,8 @@ BEGIN
   
   no_tree : IF g_nof_symbols_per_data = 1 GENERATE
     -- Capture the current accumulator values at the reload
-    nxt_sum <= truncate_or_resize_svec(acc_vec, g_sum_truncate, g_sum_w) WHEN acc_load_p = '1' ELSE i_sum;
-    
-    -- The accumulator has a latency of 1 clk cycle
-    i_sum_sync <= acc_load;
+    nxt_sum      <= truncate_or_resize_svec(acc_vec, g_sum_truncate, g_sum_w) WHEN in_sync = '1' ELSE i_sum;
+    nxt_sum_sync <= in_sync;
   END GENERATE;
   
   gen_tree : IF g_nof_symbols_per_data > 1 GENERATE
@@ -138,23 +131,21 @@ BEGIN
       sum    => acc_sum
     );
     
-    u_load_p : ENTITY common_lib.common_pipeline_sl
+    u_in_sync_p : ENTITY common_lib.common_pipeline_sl
     GENERIC MAP (
-      g_pipeline    => c_acc_sum_nof_stages*c_acc_sum_pipeline,
+      g_pipeline    => c_acc_sum_nof_stages*c_acc_sum_pipeline,  -- latency of common_adder_tree
       g_reset_value => 0
     )
     PORT MAP (
       rst     => rst,
       clk     => clk,
-      in_dat  => acc_load,
-      out_dat => acc_load_p
+      in_dat  => in_sync,
+      out_dat => in_sync_p
     );
     
-    -- Capture the current accumulator values at the reload
-    nxt_sum <= truncate_or_resize_svec(acc_sum, g_sum_truncate, g_sum_w) WHEN acc_load_p = '1' ELSE i_sum;
-    
-    -- The accumulators have a latency of 1 clk cycle 
-    i_sum_sync <= acc_load_p;
+    -- Capture the current accumulator values at the reload (taking account of the latency of common_adder_tree)
+    nxt_sum      <= truncate_or_resize_svec(acc_sum, g_sum_truncate, g_sum_w) WHEN in_sync_p = '1' ELSE i_sum;
+    nxt_sum_sync <= in_sync_p;
   END GENERATE;
  
 END rtl;

libraries/io/aduh/src/vhdl/aduh_power_sum.vhd

@@ -19,6 +19,14 @@
 --
 -------------------------------------------------------------------------------
 
+-- Purpose : Calculate the 'power' sum of input symbols during a sync interval
+-- Description :
+--   The in_data can have g_nof_symbols_per_data >= 1 per in_data word.
+--   The sync interval starts with the in_data that is valid at the in_sync.
+--   The in_data is multiplied by itself to get the power value.
+--   The output 'power' sum of the previous sync interval is valid at the
+--   sum_sync and held until the next sum_sync.
+
 LIBRARY IEEE, technology_lib, common_lib, common_mult_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE technology_lib.technology_select_pkg.ALL;
@@ -46,8 +54,7 @@ ENTITY aduh_power_sum IS
     
     -- Accumulation outputs
     pwr_sum      : OUT STD_LOGIC_VECTOR(g_pwr_sum_w-1 DOWNTO 0);
-    pwr_sum_sync : OUT STD_LOGIC;                   -- after sync there is a new sum
-    pwr_sum_sop  : OUT STD_LOGIC                    -- at    sop  there is a new sum
+    pwr_sum_sync : OUT STD_LOGIC   -- af sum_sync there is a new sum
   );
 END aduh_power_sum;
 
@@ -134,8 +141,7 @@ BEGIN
     
     -- Accumulation outputs
     sum         => pwr_sum,
-    sum_sync    => pwr_sum_sync,
-    sum_sop     => pwr_sum_sop
+    sum_sync    => pwr_sum_sync
   );
   
   -- Debug wire signal arrays for easier data interpretation in the Wave window