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Commit 2ba5d33a authored by Eric Kooistra's avatar Eric Kooistra
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On top of the tech_<component_type> level there can be yet another functional...

On top of the tech_<component_type> level there can be yet another functional level to ease the generic usage of the component in an application.
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...@@ -69,8 +69,18 @@ The mapping from technology independent tech_* component to the FPGA technology ...@@ -69,8 +69,18 @@ The mapping from technology independent tech_* component to the FPGA technology
v v v v v v v v v v
tech_ tech_ tech_ tech_ tech_ tech_ tech_ tech_ tech_ tech_
memory fifo tse transceiver tr_10GbE ... tech_<component_type> memory fifo tse transceiver tr_10GbE ... tech_<component_type>
| | | | | |
| | | | | |
v v v v v
common/ common/ io/ io/ io/
dp/ tse transceiver tr_10GbE ... io_<component_type>
... common_<component_type>
... dp_<component_type>
The tech_<component_type>_component_pkg per 'column' makes the 'column' of all IP specific implementations of the component available to the technology The tech_<component_type>_component_pkg per 'column' makes the 'column' of all IP specific implementations of the component available to the technology
independent tech_<component_type> file. The components in tech_<component_type>_component_pkg are in generic VHDL. The architecture that belongs to each independent tech_<component_type> file. The components in tech_<component_type>_component_pkg are in generic VHDL. The architecture that belongs to each
is IP dependent, but is not needed if that IP is not selected. In this way each synthesis tool only 'sees' the IP that fits the device that it supports. is IP dependent, but is not needed if that IP is not selected. In this way each synthesis tool only 'sees' the IP that fits the device that it supports.
On top of the tech_<component_type> level there can be yet another functional level to ease the generic usage of the component in an application. This
extra level typically adds useful default functionality like eg. diagnostic test functionality and FIFOs in case of a PHY IO component. It may also
contain a simulation model for the PHY IO component.
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