diff --git a/libraries/readme_libraries.txt b/libraries/readme_libraries.txt
index cb8ece31317a7c32562f43a9350358e9a1ae1803..5bd345f2cd6312be422eb9a579baf9b125b072f2 100644
--- a/libraries/readme_libraries.txt
+++ b/libraries/readme_libraries.txt
@@ -69,8 +69,18 @@ The mapping from technology independent tech_* component to the FPGA technology
                       v      v      v      v            v
                     tech_   tech_  tech_  tech_        tech_
                     memory  fifo   tse    transceiver  tr_10GbE              ... tech_<component_type>
-                    
+                      |      |      |      |            |         |
+                      |      |      |      |            |         |
+                      v      v      v      v            v
+                    common/ common/ io/    io/          io/
+                            dp/     tse    transceiver  tr_10GbE              ... io_<component_type>
+                                                                              ... common_<component_type>
+                                                                              ... dp_<component_type>
+                                                                              
 The tech_<component_type>_component_pkg per 'column' makes the 'column' of all IP specific implementations of the component available to the technology
 independent tech_<component_type> file. The components in tech_<component_type>_component_pkg are in generic VHDL. The architecture that belongs to each
 is IP dependent, but is not needed if that IP is not selected. In this way each synthesis tool only 'sees' the IP that fits the device that it supports.
-                    
\ No newline at end of file
+
+On top of the tech_<component_type> level there can be yet another functional level to ease the generic usage of the component in an application. This
+extra level typically adds useful default functionality like eg. diagnostic test functionality and FIFOs in case of a PHY IO component. It may also
+contain a simulation model for the PHY IO component.