- Added entries for 10 GbE extension

applications/apertif/designs/apertif_unb1_correlator/quartus/qsys_apertif_unb1_correlator.qsys

@@ -40,7 +40,7 @@
    {
       datum baseAddress
       {
-         value = "320";
+         value = "416";
          type = "long";
       }
    }
@@ -104,7 +104,7 @@
    {
       datum baseAddress
       {
-         value = "24576";
+         value = "32768";
          type = "long";
       }
    }
@@ -121,11 +121,19 @@
          type = "String";
       }
    }
-   element ram_diag_data_buf.mem
+   element reg_tr_10GbE.mem
+   {
+      datum baseAddress
+      {
+         value = "262144";
+         type = "long";
+      }
+   }
+   element reg_mdio_0.mem
    {
       datum baseAddress
       {
-         value = "20480";
+         value = "320";
          type = "long";
       }
    }
@@ -137,29 +145,35 @@
          type = "long";
       }
    }
-   element reg_wdi.mem
+   element reg_unb_sens.mem
    {
-      datum _lockedAddress
+      datum baseAddress
       {
-         value = "1";
-         type = "boolean";
+         value = "224";
+         type = "long";
       }
+   }
+   element reg_dp_offload_rx_hdr_dat.mem
+   {
       datum baseAddress
       {
-         value = "12288";
+         value = "512";
          type = "long";
       }
    }
-   element pio_system_info.mem
+   element ram_diag_data_buf.mem
    {
-      datum _lockedAddress
+      datum baseAddress
       {
-         value = "1";
-         type = "boolean";
+         value = "28672";
+         type = "long";
+      }
    }
+   element reg_tr_xaui.mem
+   {
       datum baseAddress
       {
-         value = "0";
+         value = "16384";
          type = "long";
       }
    }
@@ -167,15 +181,15 @@
    {
       datum baseAddress
       {
-         value = "336";
+         value = "432";
          type = "long";
       }
    }
-   element reg_unb_sens.mem
+   element reg_mdio_2.mem
    {
       datum baseAddress
       {
-         value = "224";
+         value = "288";
          type = "long";
       }
    }
@@ -192,11 +206,45 @@
          type = "long";
       }
    }
+   element reg_wdi.mem
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "12288";
+         type = "long";
+      }
+   }
+   element pio_system_info.mem
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "0";
+         type = "long";
+      }
+   }
+   element reg_mdio_1.mem
+   {
+      datum baseAddress
+      {
+         value = "256";
+         type = "long";
+      }
+   }
    element pio_pps.mem
    {
       datum baseAddress
       {
-         value = "328";
+         value = "424";
          type = "long";
       }
    }
@@ -204,7 +252,7 @@
    {
       datum baseAddress
       {
-         value = "16384";
+         value = "24576";
          type = "long";
       }
    }
@@ -283,7 +331,7 @@
       }
       datum baseAddress
       {
-         value = "256";
+         value = "352";
          type = "long";
       }
    }
@@ -291,7 +339,7 @@
    {
       datum baseAddress
       {
-         value = "304";
+         value = "400";
          type = "long";
       }
    }
@@ -327,6 +375,54 @@
          type = "int";
       }
    }
+   element reg_dp_offload_rx_hdr_dat
+   {
+      datum _sortIndex
+      {
+         value = "23";
+         type = "int";
+      }
+   }
+   element reg_mdio_0
+   {
+      datum _sortIndex
+      {
+         value = "20";
+         type = "int";
+      }
+   }
+   element reg_mdio_1
+   {
+      datum _sortIndex
+      {
+         value = "21";
+         type = "int";
+      }
+   }
+   element reg_mdio_2
+   {
+      datum _sortIndex
+      {
+         value = "22";
+         type = "int";
+      }
+   }
+   element reg_tr_10GbE
+   {
+      datum _sortIndex
+      {
+         value = "24";
+         type = "int";
+      }
+   }
+   element reg_tr_xaui
+   {
+      datum _sortIndex
+      {
+         value = "25";
+         type = "int";
+      }
+   }
    element reg_unb_sens
    {
       datum _sortIndex
@@ -351,40 +447,40 @@
          type = "int";
       }
    }
-   element pio_debug_wave.s1
+   element onchip_memory2_0.s1
    {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
       datum baseAddress
       {
-         value = "272";
+         value = "131072";
          type = "long";
       }
    }
-   element pio_wdi.s1
+   element timer_0.s1
    {
       datum baseAddress
       {
-         value = "288";
+         value = "192";
          type = "long";
       }
    }
-   element onchip_memory2_0.s1
-   {
-      datum _lockedAddress
+   element pio_debug_wave.s1
    {
-         value = "1";
-         type = "boolean";
-      }
       datum baseAddress
       {
-         value = "131072";
+         value = "368";
          type = "long";
       }
    }
-   element timer_0.s1
+   element pio_wdi.s1
    {
       datum baseAddress
       {
-         value = "192";
+         value = "384";
          type = "long";
       }
    }
@@ -416,10 +512,10 @@
  <parameter name="globalResetBus" value="false" />
  <parameter name="hdlLanguage" value="VHDL" />
  <parameter name="maxAdditionalLatency" value="0" />
- <parameter name="projectName" value="" />
+ <parameter name="projectName">apertif_unb1_correlator.qpf</parameter>
  <parameter name="sopcBorderPoints" value="false" />
  <parameter name="systemHash" value="1" />
- <parameter name="timeStamp" value="1418978186377" />
+ <parameter name="timeStamp" value="1424957033747" />
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
  <interface
@@ -1054,6 +1150,216 @@
    internal="ram_fil_coefs.readdata"
    type="conduit"
    dir="end" />
+ <interface
+   name="reg_mdio_0_reset"
+   internal="reg_mdio_0.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_0_clk"
+   internal="reg_mdio_0.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_0_address"
+   internal="reg_mdio_0.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_0_write"
+   internal="reg_mdio_0.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_0_read"
+   internal="reg_mdio_0.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_0_writedata"
+   internal="reg_mdio_0.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_0_readdata"
+   internal="reg_mdio_0.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_1_reset"
+   internal="reg_mdio_1.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_1_readdata"
+   internal="reg_mdio_1.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_1_clk"
+   internal="reg_mdio_1.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_1_address"
+   internal="reg_mdio_1.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_1_write"
+   internal="reg_mdio_1.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_1_writedata"
+   internal="reg_mdio_1.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_1_read"
+   internal="reg_mdio_1.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_2_reset"
+   internal="reg_mdio_2.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_2_clk"
+   internal="reg_mdio_2.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_2_address"
+   internal="reg_mdio_2.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_2_write"
+   internal="reg_mdio_2.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_2_writedata"
+   internal="reg_mdio_2.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_2_read"
+   internal="reg_mdio_2.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_mdio_2_readdata"
+   internal="reg_mdio_2.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_rx_hdr_dat_reset"
+   internal="reg_dp_offload_rx_hdr_dat.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_rx_hdr_dat_clk"
+   internal="reg_dp_offload_rx_hdr_dat.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_rx_hdr_dat_address"
+   internal="reg_dp_offload_rx_hdr_dat.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_rx_hdr_dat_write"
+   internal="reg_dp_offload_rx_hdr_dat.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_rx_hdr_dat_writedata"
+   internal="reg_dp_offload_rx_hdr_dat.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_rx_hdr_dat_read"
+   internal="reg_dp_offload_rx_hdr_dat.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_offload_rx_hdr_dat_readdata"
+   internal="reg_dp_offload_rx_hdr_dat.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_tr_10gbe_reset"
+   internal="reg_tr_10GbE.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_tr_10gbe_clk"
+   internal="reg_tr_10GbE.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_tr_10gbe_address"
+   internal="reg_tr_10GbE.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_tr_10gbe_write"
+   internal="reg_tr_10GbE.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_tr_10gbe_writedata"
+   internal="reg_tr_10GbE.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_tr_10gbe_read"
+   internal="reg_tr_10GbE.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_tr_10gbe_readdata"
+   internal="reg_tr_10GbE.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_tr_xaui_reset"
+   internal="reg_tr_xaui.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_tr_xaui_clk"
+   internal="reg_tr_xaui.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_tr_xaui_address"
+   internal="reg_tr_xaui.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_tr_xaui_write"
+   internal="reg_tr_xaui.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_tr_xaui_writedata"
+   internal="reg_tr_xaui.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_tr_xaui_read"
+   internal="reg_tr_xaui.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_tr_xaui_readdata"
+   internal="reg_tr_xaui.readdata"
+   type="conduit"
+   dir="end" />
  <module kind="clock_source" version="11.1" enabled="1" name="clk_0">
   <parameter name="clockFrequency" value="25000000" />
   <parameter name="clockFrequencyKnown" value="true" />
@@ -1421,7 +1727,7 @@ q]]></parameter>
   <parameter name="dcache_numTCDM" value="0" />
   <parameter name="dcache_lineSize" value="32" />
   <parameter name="instAddrWidth" value="18" />
-  <parameter name="dataAddrWidth" value="18" />
+  <parameter name="dataAddrWidth" value="19" />
   <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
   <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
   <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
@@ -1430,8 +1736,8 @@ q]]></parameter>
   <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
   <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
   <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
-  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x6000' end='0x6800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='altpll_0.pll_slave' start='0x100' end='0x110' /><slave name='pio_debug_wave.s1' start='0x110' end='0x120' /><slave name='pio_wdi.s1' start='0x120' end='0x130' /><slave name='altpll_1.pll_slave' start='0x130' end='0x140' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x140' end='0x148' /><slave name='pio_pps.mem' start='0x148' end='0x150' /><slave name='reg_diag_data_buf.mem' start='0x150' end='0x158' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='ram_fil_coefs.mem' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='ram_diag_data_buf.mem' start='0x5000' end='0x6000' /><slave name='cpu_0.jtag_debug_module' start='0x6000' end='0x6800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x8000' end='0x8800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_mdio_1.mem' start='0x100' end='0x120' /><slave name='reg_mdio_2.mem' start='0x120' end='0x140' /><slave name='reg_mdio_0.mem' start='0x140' end='0x160' /><slave name='altpll_0.pll_slave' start='0x160' end='0x170' /><slave name='pio_debug_wave.s1' start='0x170' end='0x180' /><slave name='pio_wdi.s1' start='0x180' end='0x190' /><slave name='altpll_1.pll_slave' start='0x190' end='0x1A0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1A0' end='0x1A8' /><slave name='pio_pps.mem' start='0x1A8' end='0x1B0' /><slave name='reg_diag_data_buf.mem' start='0x1B0' end='0x1B8' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x200' end='0x400' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='ram_fil_coefs.mem' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='ram_diag_data_buf.mem' start='0x7000' end='0x8000' /><slave name='cpu_0.jtag_debug_module' start='0x8000' end='0x8800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /></address-map>]]></parameter>
   <parameter name="clockFrequency" value="50000000" />
   <parameter name="deviceFamilyName" value="Stratix IV" />
   <parameter name="internalIrqMaskSystemInfo" value="7" />
@@ -1647,13 +1953,47 @@ q]]></parameter>
   <parameter name="g_dat_w" value="32" />
   <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
  </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mdio_0">
+  <parameter name="g_adr_w" value="3" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mdio_1">
+  <parameter name="g_adr_w" value="3" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mdio_2">
+  <parameter name="g_adr_w" value="3" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+   kind="avs_common_mm"
+   version="1.0"
+   enabled="1"
+   name="reg_dp_offload_rx_hdr_dat">
+  <parameter name="g_adr_w" value="7" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_tr_10GbE">
+  <parameter name="g_adr_w" value="15" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_tr_xaui">
+  <parameter name="g_adr_w" value="11" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
  <connection
    kind="avalon"
    version="11.1"
    start="cpu_0.instruction_master"
    end="cpu_0.jtag_debug_module">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x6000" />
+  <parameter name="baseAddress" value="0x8000" />
  </connection>
  <connection
    kind="avalon"
@@ -1661,7 +2001,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="cpu_0.jtag_debug_module">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x6000" />
+  <parameter name="baseAddress" value="0x8000" />
  </connection>
  <connection
    kind="avalon"
@@ -1685,7 +2025,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="jtag_uart_0.avalon_jtag_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0140" />
+  <parameter name="baseAddress" value="0x01a0" />
  </connection>
  <connection
    kind="interrupt"
@@ -1700,7 +2040,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="altpll_0.pll_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0100" />
+  <parameter name="baseAddress" value="0x0160" />
  </connection>
  <connection kind="clock" version="11.1" start="altpll_0.c0" end="cpu_0.clk" />
  <connection
@@ -1725,7 +2065,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="pio_debug_wave.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0110" />
+  <parameter name="baseAddress" value="0x0170" />
  </connection>
  <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_wdi.clk" />
  <connection
@@ -1734,7 +2074,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="pio_wdi.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0120" />
+  <parameter name="baseAddress" value="0x0180" />
  </connection>
  <connection kind="clock" version="11.1" start="altpll_0.c0" end="timer_0.clk" />
  <connection
@@ -1794,7 +2134,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="pio_pps.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0148" />
+  <parameter name="baseAddress" value="0x01a8" />
  </connection>
  <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_wdi.system" />
  <connection
@@ -1828,7 +2168,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="avs_eth_0.mms_ram">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x4000" />
+  <parameter name="baseAddress" value="0x6000" />
  </connection>
  <connection
    kind="interrupt"
@@ -1989,7 +2329,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="ram_diag_data_buf.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x5000" />
+  <parameter name="baseAddress" value="0x7000" />
  </connection>
  <connection
    kind="avalon"
@@ -1997,7 +2337,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="reg_diag_data_buf.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0150" />
+  <parameter name="baseAddress" value="0x01b0" />
  </connection>
  <connection
    kind="clock"
@@ -2015,7 +2355,7 @@ q]]></parameter>
    start="cpu_0.data_master"
    end="altpll_1.pll_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0130" />
+  <parameter name="baseAddress" value="0x0190" />
  </connection>
  <connection
    kind="clock"
@@ -2040,4 +2380,112 @@ q]]></parameter>
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x3800" />
  </connection>
+ <connection
+   kind="clock"
+   version="11.1"
+   start="altpll_0.c0"
+   end="reg_mdio_0.system" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="altpll_0.c0"
+   end="reg_mdio_1.system" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="altpll_0.c0"
+   end="reg_mdio_2.system" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="altpll_0.c0"
+   end="reg_dp_offload_rx_hdr_dat.system" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="altpll_0.c0"
+   end="reg_tr_10GbE.system" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="altpll_0.c0"
+   end="reg_tr_xaui.system" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="reg_mdio_0.system_reset" />
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="reg_mdio_1.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0100" />
+ </connection>
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="reg_mdio_1.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="reg_mdio_2.system_reset" />
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="reg_mdio_2.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0120" />
+ </connection>
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="reg_dp_offload_rx_hdr_dat.system_reset" />
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="reg_dp_offload_rx_hdr_dat.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0200" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="reg_tr_10GbE.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00040000" />
+ </connection>
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="reg_tr_10GbE.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="reg_tr_xaui.system_reset" />
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="reg_tr_xaui.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x4000" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="reg_mdio_0.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0140" />
+ </connection>
 </system>