Skip to content
Snippets Groups Projects
Commit 955f5b27 authored by Pepping's avatar Pepping
Browse files

Added 10 GbE Receiver.

Added de- and reinterleavers. 
Reorganized the order of constants and signals. 
Updated paths with new "designs" level.
parent 97008a4b
No related branches found
No related tags found
No related merge requests found
...@@ -102,7 +102,7 @@ ARCHITECTURE str OF apertif_unb1_correlator IS ...@@ -102,7 +102,7 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
-- Firmware version x.y -- Firmware version x.y
CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 1); CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 1);
-- Enable block generators -- Enable block generators
CONSTANT c_use_bg : BOOLEAN := FALSE; CONSTANT c_use_bg : BOOLEAN := g_sim;
-- In simulation we don't need the 1GbE core for MM control, deselect it in c_use_phy based on g_sim -- In simulation we don't need the 1GbE core for MM control, deselect it in c_use_phy based on g_sim
CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(g_sim, 0, 1), sel_a_b(c_use_bg, 0, 1), 0, 0, 0, 0, 0, 1); CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(g_sim, 0, 1), sel_a_b(c_use_bg, 0, 1), 0, 0, 0, 0, 0, 1);
...@@ -110,6 +110,67 @@ ARCHITECTURE str OF apertif_unb1_correlator IS ...@@ -110,6 +110,67 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
CONSTANT c_nof_bf_modules : NATURAL := c_bf.nof_bf_units; -- We have 4 BF modules here because each sending fn_beamformer design has 4 bf units. CONSTANT c_nof_bf_modules : NATURAL := c_bf.nof_bf_units; -- We have 4 BF modules here because each sending fn_beamformer design has 4 bf units.
CONSTANT c_compl_dat_w : NATURAL := 8; CONSTANT c_compl_dat_w : NATURAL := 8;
-- BSN Alignern + FIFO's
CONSTANT c_block_period : NATURAL := 256;
CONSTANT c_block_size : NATURAL := 176;
CONSTANT c_bsn_align_latency : NATURAL := 3;
CONSTANT c_bsn_align_sop_timeout : NATURAL := (c_bsn_align_latency + 1) * c_block_period; -- wait somewhat more than c_bsn_align_latency periods
CONSTANT c_bsn_align_xoff_timeout : NATURAL := c_bsn_align_latency * 2 * c_block_period; -- flush factor 2 longer than needed
CONSTANT c_dp_fifo_size : NATURAL := (c_bsn_align_latency + 5) * c_block_size; -- be able to fit blocks for as long as sop time out;
CONSTANT c_dp_fifo_fill : NATURAL := c_block_size;
-- Re- and Deinterleaver
CONSTANT c_use_complex : BOOLEAN := TRUE;
-- Correlator
CONSTANT c_nof_inputs : NATURAL := sel_a_b(g_sim, 24, 24);
CONSTANT c_nof_input_folds : NATURAL := 1;
CONSTANT c_nof_input_streams : NATURAL := c_nof_inputs / pow2(c_nof_input_folds);
CONSTANT c_nof_pre_mult_folds : NATURAL := 1;
CONSTANT c_complex_data_w : NATURAL := 8;
CONSTANT c_conjugate : BOOLEAN := TRUE;
CONSTANT c_nof_channels : NATURAL := 64;
CONSTANT c_integration_period : NATURAL := sel_a_b(g_sim, 0, 12208);
CONSTANT c_nof_visibilities : NATURAL := (c_nof_inputs*(c_nof_inputs+1))/2;
-- WPFB
CONSTANT c_wpfb_wb_factor : NATURAL := 1; -- = default 1, wideband factor
CONSTANT c_wpfb_nof_wb_streams : NATURAL := c_nof_input_streams; -- = 1, the number of parallel wideband streams. The fi
CONSTANT c_wpfb_nof_chan : NATURAL := 1; -- = default 0, defines the number of channels (=time-m
CONSTANT c_wpfb_nof_points : NATURAL := 64; -- = 1024, N point FFT
CONSTANT c_wpfb_nof_taps : NATURAL := 8; -- = 8 nof taps n the filter
CONSTANT c_wpfb_in_dat_w : NATURAL := 8; --6; -- = 8, number of input bits
CONSTANT c_wpfb_out_dat_w : NATURAL := 14; --12; -- = 14, number of output bits: in_dat_w + natural((cei
CONSTANT c_wpfb_use_separate : BOOLEAN := FALSE; -- = false for complex input, true for two real inputs
CONSTANT c_wpfb_use_reorder : BOOLEAN := FALSE;
CONSTANT c_wpfb : t_wpfb := (c_wpfb_wb_factor, c_wpfb_nof_points, c_wpfb_nof_chan, c_wpfb_nof_wb_streams,
c_wpfb_nof_taps, c_wpfb_in_dat_w, 16, 16,
c_wpfb_use_reorder, c_wpfb_use_separate, 16, c_wpfb_out_dat_w, 18, 2, true, 56, 2,
c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
CONSTANT c_wpfb_coefs_file_prefix : STRING := "../../../../../UniBoard/trunk/Firmware/dsp/filter/build/data/coefs_wide1_p64_t8";
-- Block generator
CONSTANT c_bg_block_size : NATURAL := c_nof_channels*pow2(c_nof_input_folds);
CONSTANT c_bg_gapsize : NATURAL := 0;
-- Indicate the integration period with the sync. In the correlator, the
-- integration period is forced to a minimum of c_nof_visibilities to
-- allow folding the output onto one stream.
-- . The sync pulse is only there for the human eye (wave window) -
-- it is not used by the correlator.
CONSTANT c_bg_blocks_per_sync : NATURAL := largest(c_integration_period, c_nof_visibilities);
CONSTANT c_bg_ctrl : t_diag_block_gen := ('1', -- enable
'0', -- enable_sync
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
TO_UVEC( 0, c_diag_bg_bsn_init_w));
-- System -- System
SIGNAL cs_sim : STD_LOGIC; SIGNAL cs_sim : STD_LOGIC;
SIGNAL xo_clk : STD_LOGIC; SIGNAL xo_clk : STD_LOGIC;
...@@ -126,25 +187,25 @@ ARCHITECTURE str OF apertif_unb1_correlator IS ...@@ -126,25 +187,25 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
-- PIOs -- PIOs
SIGNAL pout_wdi : STD_LOGIC; SIGNAL pout_wdi : STD_LOGIC;
-- WDI override -- MM WDI override
SIGNAL reg_wdi_mosi : t_mem_mosi; SIGNAL reg_wdi_mosi : t_mem_mosi;
SIGNAL reg_wdi_miso : t_mem_miso; SIGNAL reg_wdi_miso : t_mem_miso;
-- PPSH -- MM PPSH
SIGNAL reg_ppsh_mosi : t_mem_mosi; SIGNAL reg_ppsh_mosi : t_mem_mosi;
SIGNAL reg_ppsh_miso : t_mem_miso; SIGNAL reg_ppsh_miso : t_mem_miso;
-- UniBoard system info -- MM UniBoard system info
SIGNAL reg_unb_system_info_mosi : t_mem_mosi; SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
SIGNAL reg_unb_system_info_miso : t_mem_miso; SIGNAL reg_unb_system_info_miso : t_mem_miso;
SIGNAL rom_unb_system_info_mosi : t_mem_mosi; SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
SIGNAL rom_unb_system_info_miso : t_mem_miso; SIGNAL rom_unb_system_info_miso : t_mem_miso;
-- UniBoard I2C sens -- MM UniBoard I2C sens
SIGNAL reg_unb_sens_mosi : t_mem_mosi; SIGNAL reg_unb_sens_mosi : t_mem_mosi;
SIGNAL reg_unb_sens_miso : t_mem_miso; SIGNAL reg_unb_sens_miso : t_mem_miso;
-- eth1g -- MM eth1g
SIGNAL eth1g_tse_clk : STD_LOGIC; SIGNAL eth1g_tse_clk : STD_LOGIC;
SIGNAL eth1g_mm_rst : STD_LOGIC; SIGNAL eth1g_mm_rst : STD_LOGIC;
SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
...@@ -155,6 +216,20 @@ ARCHITECTURE str OF apertif_unb1_correlator IS ...@@ -155,6 +216,20 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
SIGNAL eth1g_ram_miso : t_mem_miso; SIGNAL eth1g_ram_miso : t_mem_miso;
-- MM DP offload RX
SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
-- MM Filterbank
SIGNAL ram_fil_coefs_mosi : t_mem_mosi;
SIGNAL ram_fil_coefs_miso : t_mem_miso;
-- MM Databuffer
SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_miso : t_mem_miso;
-- Interface: 10GbE -- Interface: 10GbE
SIGNAL xaui_tx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0); SIGNAL xaui_tx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL xaui_rx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0); SIGNAL xaui_rx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0);
...@@ -170,94 +245,32 @@ ARCHITECTURE str OF apertif_unb1_correlator IS ...@@ -170,94 +245,32 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0); SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0); SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
-- DP offload -- DP offload RX
SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0); SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0); SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0); SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy); SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
SIGNAL dp_offload_rx_restored_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst); SIGNAL dp_offload_rx_restored_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_10GbE_streams-1 DOWNTO 0); SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_10GbE_streams-1 DOWNTO 0);
-- BSN Alignern + FIFO's -- BSN Aligner
CONSTANT c_block_period : NATURAL := 256;
CONSTANT c_block_size : NATURAL := 176;
CONSTANT c_bsn_align_latency : NATURAL := 3;
CONSTANT c_bsn_align_sop_timeout : NATURAL := (c_bsn_align_latency + 1) * c_block_period; -- wait somewhat more than c_bsn_align_latency periods
CONSTANT c_bsn_align_xoff_timeout : NATURAL := c_bsn_align_latency * 2 * c_block_period; -- flush factor 2 longer than needed
CONSTANT c_dp_fifo_size : NATURAL := (c_bsn_align_latency + 5) * c_block_size; -- be able to fit blocks for as long as sop time out;
CONSTANT c_dp_fifo_fill : NATURAL := c_block_size;
SIGNAL dp_fifo_fill_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0); SIGNAL dp_fifo_fill_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_fifo_fill_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0); SIGNAL dp_fifo_fill_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_bsn_align_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy); SIGNAL dp_bsn_align_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
SIGNAL dp_bsn_align_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0); SIGNAL dp_bsn_align_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
-- Correlator -- De and Reinterleaver
CONSTANT c_nof_inputs : NATURAL := sel_a_b(g_sim, 24, 24); SIGNAL interleaved_arr : t_dp_sosi_arr(c_nof_10GbE_streams*c_nof_bf_modules-1 DOWNTO 0);
CONSTANT c_nof_input_folds : NATURAL := 1; SIGNAL deinterleaved_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
CONSTANT c_nof_input_streams : NATURAL := c_nof_inputs / pow2(c_nof_input_folds); SIGNAL reinterleave_in_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
CONSTANT c_nof_pre_mult_folds : NATURAL := 1; SIGNAL reinterleave_out_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
CONSTANT c_complex_data_w : NATURAL := 8;
CONSTANT c_conjugate : BOOLEAN := TRUE;
CONSTANT c_nof_channels : NATURAL := 64;
CONSTANT c_integration_period : NATURAL := sel_a_b(g_sim, 0, 12208);
CONSTANT c_nof_visibilities : NATURAL := (c_nof_inputs*(c_nof_inputs+1))/2;
-- WPFB
CONSTANT c_wpfb_wb_factor : NATURAL := 1; -- = default 1, wideband factor
CONSTANT c_wpfb_nof_wb_streams : NATURAL := c_nof_input_streams; -- = 1, the number of parallel wideband streams. The fi
CONSTANT c_wpfb_nof_chan : NATURAL := 1; -- = default 0, defines the number of channels (=time-m
CONSTANT c_wpfb_nof_points : NATURAL := 64; -- = 1024, N point FFT
CONSTANT c_wpfb_nof_taps : NATURAL := 8; -- = 8 nof taps n the filter
CONSTANT c_wpfb_in_dat_w : NATURAL := 8; --6; -- = 8, number of input bits
CONSTANT c_wpfb_out_dat_w : NATURAL := 14; --12; -- = 14, number of output bits: in_dat_w + natural((cei
CONSTANT c_wpfb_use_separate : BOOLEAN := FALSE; -- = false for complex input, true for two real inputs
CONSTANT c_wpfb_use_reorder : BOOLEAN := FALSE;
CONSTANT c_wpfb : t_wpfb := (c_wpfb_wb_factor, c_wpfb_nof_points, c_wpfb_nof_chan, c_wpfb_nof_wb_streams,
c_wpfb_nof_taps, c_wpfb_in_dat_w, 16, 16,
c_wpfb_use_reorder, c_wpfb_use_separate, 16, c_wpfb_out_dat_w, 18, 2, true, 56, 2,
c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
CONSTANT c_wpfb_coefs_file_prefix : STRING := "../../../../../UniBoard/trunk/Firmware/dsp/filter/build/data/coefs_wide1_p64_t8";
-- Block generator
CONSTANT c_bg_block_size : NATURAL := c_nof_channels*pow2(c_nof_input_folds);
CONSTANT c_bg_gapsize : NATURAL := 0;
-- Indicate the integration period with the sync. In the correlator, the
-- integration period is forced to a minimum of c_nof_visibilities to
-- allow folding the output onto one stream.
-- . The sync pulse is only there for the human eye (wave window) -
-- it is not used by the correlator.
CONSTANT c_bg_blocks_per_sync : NATURAL := largest(c_integration_period, c_nof_visibilities);
CONSTANT c_bg_ctrl : t_diag_block_gen := ('1', -- enable
'0', -- enable_sync
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
TO_UVEC( 0, c_diag_bg_bsn_init_w));
-- Filterbank and Correalator
SIGNAL wpfb_snk_in_ctrl : t_dp_sosi;
SIGNAL wpfb_snk_in_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0); SIGNAL wpfb_snk_in_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
SIGNAL wpfb_src_out_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0); SIGNAL wpfb_src_out_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
SIGNAL correlator_src_out_arr : t_dp_sosi_arr(1-1 DOWNTO 0); SIGNAL correlator_src_out_arr : t_dp_sosi_arr(1-1 DOWNTO 0);
SIGNAL ram_fil_coefs_mosi : t_mem_mosi;
SIGNAL ram_fil_coefs_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_miso : t_mem_miso;
BEGIN BEGIN
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -269,7 +282,7 @@ BEGIN ...@@ -269,7 +282,7 @@ BEGIN
g_nof_output_streams => c_nof_input_streams, g_nof_output_streams => c_nof_input_streams,
g_buf_dat_w => 2*c_complex_data_w, g_buf_dat_w => 2*c_complex_data_w,
g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)), g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
g_file_name_prefix => "../../../applications/apertif/apertif_unb1_correlator/src/hex/composite_signals", g_file_name_prefix => "../../../applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals",
g_diag_block_gen_rst => c_bg_ctrl g_diag_block_gen_rst => c_bg_ctrl
) )
PORT MAP ( PORT MAP (
...@@ -279,7 +292,7 @@ BEGIN ...@@ -279,7 +292,7 @@ BEGIN
dp_rst => dp_rst, dp_rst => dp_rst,
dp_clk => dp_clk, dp_clk => dp_clk,
out_sosi_arr => wpfb_snk_in_arr out_sosi_arr => interleaved_arr
); );
END GENERATE; END GENERATE;
...@@ -483,19 +496,86 @@ BEGIN ...@@ -483,19 +496,86 @@ BEGIN
BEGIN BEGIN
FOR i IN 0 TO c_nof_10GbE_streams-1 LOOP FOR i IN 0 TO c_nof_10GbE_streams-1 LOOP
FOR j IN 0 TO c_nof_bf_modules-1 LOOP FOR j IN 0 TO c_nof_bf_modules-1 LOOP
-- dp_bsn_align_src_out_2arr(i)(j) <= dp_bsn_align_src_out_arr(i); -- SOSI ctrl interleaved_arr(i*c_nof_bf_modules + j) <= dp_bsn_align_src_out_arr(i); -- SOSI ctrl
-- dp_bsn_align_src_out_2arr(i)(j).data <= (OTHERS=>'0'); interleaved_arr(i*c_nof_bf_modules + j).data <= (OTHERS=>'0');
-- dp_bsn_align_src_out_2arr(i)(j).im <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w+c_compl_dat_w DOWNTO c_nof_complex*j*c_compl_dat_w+c_compl_dat_w)); interleaved_arr(i*c_nof_bf_modules + j).im <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w+c_compl_dat_w DOWNTO c_nof_complex*j*c_compl_dat_w+c_compl_dat_w));
-- dp_bsn_align_src_out_2arr(i)(j).re <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w-1 DOWNTO c_nof_complex*j*c_compl_dat_w)); interleaved_arr(i*c_nof_bf_modules + j).re <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w-1 DOWNTO c_nof_complex*j*c_compl_dat_w));
END LOOP;
wpfb_snk_in_arr(i*c_nof_bf_modules + j) <= dp_bsn_align_src_out_arr(i); -- SOSI ctrl END LOOP;
wpfb_snk_in_arr(i*c_nof_bf_modules + j).data <= (OTHERS=>'0'); END PROCESS;
wpfb_snk_in_arr(i*c_nof_bf_modules + j).im <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w+c_compl_dat_w DOWNTO c_nof_complex*j*c_compl_dat_w+c_compl_dat_w)); END GENERATE;
wpfb_snk_in_arr(i*c_nof_bf_modules + j).re <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w-1 DOWNTO c_nof_complex*j*c_compl_dat_w));
gen_deinterleave : FOR i IN 0 TO c_nof_10GbE_streams*c_nof_bf_modules-1 GENERATE
u_deinterleave : ENTITY dp_lib.dp_deinterleave
GENERIC MAP (
g_nof_out => 2,
g_block_size => 1,
g_dat_w => c_nof_complex*c_wpfb_in_dat_w,
g_use_ctrl => FALSE,
g_align_out => TRUE,
g_use_complex => c_use_complex
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
snk_in => interleaved_arr(i),
src_out_arr => deinterleaved_arr(2*i+1 DOWNTO 2*i)
);
END GENERATE;
p_reorder_array : PROCESS(deinterleaved_arr)
BEGIN
FOR i IN 0 TO 2*c_nof_bf_modules-1 LOOP
FOR j IN 0 TO c_nof_10GbE_streams-1 LOOP
reinterleave_in_arr(i*c_nof_10GbE_streams + j) <= deinterleaved_arr(j*2*c_nof_bf_modules + i);
END LOOP; END LOOP;
END LOOP; END LOOP;
END PROCESS; END PROCESS;
gen_reinterleave : FOR i IN 0 TO c_nof_10GbE_streams*c_nof_bf_modules-1 GENERATE
u_reinterleave : ENTITY dp_lib.dp_reinterleave
GENERIC MAP (
g_nof_in => 2,
g_deint_block_size => 1,
g_nof_out => 1,
g_inter_block_size => 1,
g_use_ctrl => FALSE,
g_dat_w => c_nof_complex*c_wpfb_in_dat_w,
g_use_complex => c_use_complex,
g_align_out => TRUE
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
snk_in_arr => reinterleave_in_arr(2*i+1 DOWNTO 2*i),
src_out_arr => reinterleave_out_arr(i DOWNTO i)
);
END GENERATE; END GENERATE;
u_st_ctrl_pipe : ENTITY dp_lib.dp_pipeline
GENERIC MAP(
g_pipeline => 3 -- 0 for wires, > 0 for registers,
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
-- ST sink
snk_in => interleaved_arr(0),
-- ST source
src_out => wpfb_snk_in_ctrl
);
p_add_st_ctrl : PROCESS(reinterleave_out_arr, wpfb_snk_in_ctrl)
BEGIN
FOR i IN 0 TO c_nof_input_streams-1 LOOP
wpfb_snk_in_arr(i) <= wpfb_snk_in_ctrl; -- SOSI ctrl
wpfb_snk_in_arr(i).data <= reinterleave_out_arr(i).data;
wpfb_snk_in_arr(i).im <= reinterleave_out_arr(i).im;
wpfb_snk_in_arr(i).re <= reinterleave_out_arr(i).re;
END LOOP;
END PROCESS;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- WPFB -- WPFB
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -532,7 +612,7 @@ BEGIN ...@@ -532,7 +612,7 @@ BEGIN
g_sim => TRUE, g_sim => TRUE,
g_pass_through => FALSE, g_pass_through => FALSE,
g_rec_not_play => TRUE, g_rec_not_play => TRUE,
g_rec_play_file => "../../../applications/apertif/apertif_unb1_correlator/tb/rec/wpfb_src_out_arr0.rec", g_rec_play_file => "../../../applications/apertif/designs/apertif_unb1_correlator/tb/rec/wpfb_src_out_arr0.rec",
g_record_invalid => FALSE g_record_invalid => FALSE
) )
PORT MAP ( PORT MAP (
...@@ -573,7 +653,7 @@ BEGIN ...@@ -573,7 +653,7 @@ BEGIN
g_sim => TRUE, g_sim => TRUE,
g_pass_through => FALSE, g_pass_through => FALSE,
g_rec_not_play => TRUE, g_rec_not_play => TRUE,
g_rec_play_file => "../../../applications/apertif/apertif_unb1_correlator/tb/rec/correlator_src_out_arr0.rec", g_rec_play_file => "../../../applications/apertif/designs/apertif_unb1_correlator/tb/rec/correlator_src_out_arr0.rec",
g_record_invalid => FALSE g_record_invalid => FALSE
) )
PORT MAP ( PORT MAP (
...@@ -744,6 +824,18 @@ BEGIN ...@@ -744,6 +824,18 @@ BEGIN
reg_ppsh_mosi => reg_ppsh_mosi, reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso, reg_ppsh_miso => reg_ppsh_miso,
-- 10 GbE
reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
reg_tr_10GbE_miso => reg_tr_10GbE_miso,
reg_tr_xaui_mosi => reg_tr_xaui_mosi,
reg_tr_xaui_miso => reg_tr_xaui_miso,
reg_mdio_mosi_arr => reg_mdio_mosi_arr,
reg_mdio_miso_arr => reg_mdio_miso_arr,
-- DP offload RX
reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-- . Data buffers -- . Data buffers
reg_diag_data_buf_mosi => reg_diag_data_buf_mosi, reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
reg_diag_data_buf_miso => reg_diag_data_buf_miso, reg_diag_data_buf_miso => reg_diag_data_buf_miso,
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment