CWG-44, fixed merge failure

.gitlab-ci.yml

@@ -26,7 +26,6 @@
 # . See https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+Gitlab+pipeline+automation+to+test+SDPFW+with+OPC+UA
 
 stages:
-    - linting
     - simulation
     - synthesis
     - hardware
@@ -52,7 +51,7 @@ lint-vhdl-lib-dsp:
     script:
         - cd libraries/dsp
         - find . -name "*.vhd" -exec vsg -c ../../vsg_config.yaml -f {} \;
-      
+
 lint-vhdl-lib-io:
     tags:
         - hdl
@@ -63,7 +62,7 @@ lint-vhdl-lib-io:
     script:
         - cd libraries/io
         - find . -name "*.vhd" -exec vsg -c ../../vsg_config.yaml -f {} \;
-      
+
 lint-vhdl-lib-technology:
     tags:
         - hdl
@@ -112,7 +111,7 @@ lint-vhdl-applications-lofar2:
 # HDL simulation stage
 ###############################################################################
 sim-compile:
-    tags: 
+    tags:
         - fpga
     stage: simulation
     script:
@@ -124,12 +123,12 @@ sim-compile:
             - build/
 
 sim-run:
-    tags: 
+    tags:
         - fpga
     stage: simulation
     script:
         - echo "Running simulations"
-#        - test -f "build/info.txt" # This fails despite having artifact (see 
+#        - test -f "build/info.txt" # This fails despite having artifact (see
                                     # sim-compile code block where a folder and
                                     # file are generated and preserved by using
                                     # 'artifacts').
@@ -138,21 +137,21 @@ sim-run:
 # HDL synthesis stage
 ###############################################################################
 synth-compile:
-    tags: 
+    tags:
         - fpga
     stage: synthesis
     script:
         - echo "Compiling for synthesis"
 
 synth-check-fmax:
-    tags: 
+    tags:
         - fpga
     stage: synthesis
     script:
         - echo "Checking achieved fMax"
 
 synth-check-programming-files:
-    tags: 
+    tags:
         - fpga
     stage: synthesis
     script: