diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 3eec78441255290a23c74d00c8305dc22868c791..b4e4f5a75e93b8eab50b50083b2a23f578f33c12 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -26,7 +26,6 @@
# . See https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+Gitlab+pipeline+automation+to+test+SDPFW+with+OPC+UA
stages:
- - linting
- simulation
- synthesis
- hardware
@@ -52,7 +51,7 @@ lint-vhdl-lib-dsp:
script:
- cd libraries/dsp
- find . -name "*.vhd" -exec vsg -c ../../vsg_config.yaml -f {} \;
-
+
lint-vhdl-lib-io:
tags:
- hdl
@@ -63,7 +62,7 @@ lint-vhdl-lib-io:
script:
- cd libraries/io
- find . -name "*.vhd" -exec vsg -c ../../vsg_config.yaml -f {} \;
-
+
lint-vhdl-lib-technology:
tags:
- hdl
@@ -112,7 +111,7 @@ lint-vhdl-applications-lofar2:
# HDL simulation stage
###############################################################################
sim-compile:
- tags:
+ tags:
- fpga
stage: simulation
script:
@@ -124,12 +123,12 @@ sim-compile:
- build/
sim-run:
- tags:
+ tags:
- fpga
stage: simulation
script:
- echo "Running simulations"
-# - test -f "build/info.txt" # This fails despite having artifact (see
+# - test -f "build/info.txt" # This fails despite having artifact (see
# sim-compile code block where a folder and
# file are generated and preserved by using
# 'artifacts').
@@ -138,21 +137,21 @@ sim-run:
# HDL synthesis stage
###############################################################################
synth-compile:
- tags:
+ tags:
- fpga
stage: synthesis
script:
- echo "Compiling for synthesis"
synth-check-fmax:
- tags:
+ tags:
- fpga
stage: synthesis
script:
- echo "Checking achieved fMax"
synth-check-programming-files:
- tags:
+ tags:
- fpga
stage: synthesis
script:
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt b/applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt
index c90a88688f9bf3c446042e7567287b4b5c63c4d8..9a54def39092dd7ed5021298802a2956d79552a0 100644
--- a/applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt
@@ -7,8 +7,9 @@ Detailed design: Transient Buffer (TBuf) function for LIFT project
3) TBB (Transient Buffer Board) LOFAR1
4) TBuf (Transient Buffer) Design
5) TBuf ICD SC-SDP, SDPTR-SDPFW
-6) TBuf ICD STAT/SDP-CEP
-7) Crossbar
+6) SC / dump tool operation
+7) TBuf ICD STAT/SDP-CEP
+8) Crossbar
10) Planning
11) Transient detection (TDet) Design
@@ -253,107 +254,124 @@ The CP FPGA_beamlet_output_nof_beamlets_RW is not supported in SDPTR and SDPFW y
* In LOFAR1 bepaald LCU welke si uitgelezen moet worden richting CEP. De
TBB uP zorgt dan dat de nof pages verstuurd worden.
* Only FPGA_TBuf CP and MP. No need for TR_tbuf CP or MP
+* SDPTR translates between double float timestamp = integer RSN * T_adc
- Control Points (CP) en Monitor Points (MP):
* Raw data:
. W_adc = 14b, always use all ADC bits, so no need for W_raw.
. W_ant = N_pol * W_adc = 28b
- . c_tbuf_raw_sample_period
- = 5 ns at FPGA_sdp_info_f_adc_R = 200 MHz
- = 6.25 ns at FPGA_sdp_info_f_adc_R = 160 MHz
+ . SDPTR: raw sample period T_adc from FPGA_sdp_info_f_adc_R:
+ T_adc = 5 ns at FPGA_sdp_info_f_adc_R = 200 MHz
+ T_adc = 6.25 ns at FPGA_sdp_info_f_adc_R = 160 MHz
- * RSN source (dp_rsn_source with nof_clk_per_sync register)
+ * RSN source (= dp_rsn_source.vhd)
FPGA_processing_enable_RW
- . SDPTR: set tbuf_nof_clk_per_sync dependent on FPGA_sdp_info_f_adc_R
- . SDPFW: start RSN source at BSN sync, RSN derived from BSN
+ . SDPTR: sets nof_clk_per_sync in mms_dp_bsn_source.vhd dependent on FPGA_sdp_info_f_adc_R
+ . SDPFW: no need for MM interface:
+ use nof_clk_per_sync from dp_bsn_source also for dp_rsn_source
+ start RSN source when dp_bsn_source is (re)started, derive RSN from BSN
. c_tbuf_nof_samples_per_block =
c_tbuf_nof_samples_per_page =
c_tbuf_nof_samples_per_packet = 2000
- . tbuf_nof_block_per_sync = tbuf_nof_clk_per_sync / c_tbuf_nof_samples_per_packet
+ . nof_block_per_sync = nof_clk_per_sync / c_tbuf_nof_samples_per_packet
= 100k for sync interval 1 s at FPGA_sdp_info_f_adc_R = 200 MHz
= 80k for sync interval 1 s at FPGA_sdp_info_f_adc_R = 160 MHz
* RSN monitor (dp_bsn_monitor)
- . FPGA_tbuf_signal_input_timestamp_R = FPGA_tbuf_signal_input_rsn_R * raw_sample_period
. FPGA_tbuf_signal_input_rsn_R = RSN at sync
- FPGA_tbuf_signal_input_nof_blocks_R : expected value tbuf_nof_block_per_sync
- FPGA_tbuf_signal_input_nof_samples_R : expected value tbuf_nof_clk_per_sync
+ FPGA_tbuf_signal_input_nof_blocks_R : expected value nof_block_per_sync = 100k or 80k
+ FPGA_tbuf_signal_input_nof_samples_R : expected value nof_clk_per_sync = 200M or 160M
* Record:
. FPGA_tbuf_record_all_RW[pn]
True = record all antenna inputs,
- False = record only half of the antenna inputs, the once that have even index.
+ False = record only half of the antenna inputs, the half that have even index.
. FPGA_tbuf_record_enable_RW[pn]
- True = start/continue,
+ FPGA_tbuf_record_enable_R[pn]
+ True = start/continue recording, all ai or half of ai (dependent on FPGA_tbuf_record_all_RW)
False = stop/freeze recording immediately
* Recording:
- . FPGA_tbuf_recording_R[pn]
- True = pn is recording, all ai or half of ai (dependent on FPGA_tbuf_record_all_RW)
- False = pn is frozen
-
- . FPGA_tbuf_recorded_last_timestamp_R[pn] = recorded_last_rsn * raw_sample_period
- . FPGA_tbuf_recorded_first_timestamp_R[pn] = recorded_first_rsn * raw_sample_period
- . FPGA_tbuf_recorded_time_interval_R[pn] = FPGA_tbuf_recorded_last_timestamp_R - FPGA_tbuf_recorded_first_timestamp_R
- While FPGA_tbuf_recording_R = True then the last and first timestamps will increment in time
- After the circular buffer has filled, then the time_interval will remain fixed at maximum.
+ . FPGA_tbuf_recorded_last_timestamp_R[pn] = reg_recorded_last_rsn_R * T_adc
+ . FPGA_tbuf_recorded_first_timestamp_R[pn] = reg_recorded_first_rsn_R * T_adc
+ . FPGA_tbuf_recorded_time_interval_R[pn] = (reg_recorded_last_rsn_R - reg_recorded_first_rsn_R) * T_adc
+ While FPGA_tbuf_record_enable_R = True then the last timestamp will increment in time and
+ the first timestamp will remain constant until the circular buffer has filled once.
+ After that the first timestamp will also increment in time, and the time_interval
+ between first and last will remain fixed at maximum buffer time.
* Dumping:
- . FPGA_tbuf_dump_inter_packet_gap_RW --> wait time between packets send to CEP in raw_sample_period units
- . FPGA_tbuf_dump_timestamp_range_RW[pn][start, end]
- [0] = start timestamp,
- [1] = end timestamp
- SDPTR translates between float timestamp = integer RSN * raw_sample_period
+ . FPGA_tbuf_dump_inter_packet_time_RW
+ Wait time in seconds between packets send to CEP. SDPTR translates float time into
+ T_adc units.
+
+ . FPGA_tbuf_dump_start_timestamp_RW[pn]
+ FPGA_tbuf_dump_start_timestamp_R[pn] = reg_dump_start_rsn_RW * T_adc
+ Timestamp of first packet that will be dumped. Equals FPGA_tbuf_dump_start_timestamp_RW
+ if it exists in the buffer.
+ . FPGA_tbuf_dump_end_timestamp_RW[pn]
+ FPGA_tbuf_dump_end_timestamp_R[pn]
+ Timestamp of last packet that will be dumped. Equals FPGA_tbuf_dump_end_timestamp_RW
+ if it exists in the buffer.
+ . FPGA_tbuf_dump_nof_packets_R[pn] = reg_dump_nof_pages_RW
+ Amount of packets that will be dumped for range that is requested via FPGA_tbuf_dump_start_timestamp_RW
+ and FPGA_tbuf_dump_end_timestamp_RW. Forced to 0 if requested tange is not in buffer.
+ Each packet contains c_tbuf_nof_samples_per_packet = 2000 raw samples. This corresponds
+ to c_tbuf_nof_samples_per_packet * T_adc = 2000 * 5 ns = 10 us or 2000 * 6.25 ns = 12.5 us
+ of raw sample data per packet. Hence it takes about 100 packets to transport 1 ms of
+ raw sample data for one antenna input, and about 100000 packets to transport 1 s.
+
. FPGA_tbuf_dump_enable_RW[pn][ai]
- True = start / keep dumping packets for the requested ai,
- False = stop dumping
+ FPGA_tbuf_dump_enable_R[pn][ai] = value of FPGA_tbuf_dump_enable_RW in SDPFW
+ True = start / keep dumping packets for the requested ai, dumping stops when all
+ packets have been dumped, it is not necessary to explicitely stop the dumping.
+ - when busy then FPGA_tbuf_memory_read_nof_packets_R increments until it reaches value of
+ FPGA_tbuf_dump_nof_packets_R
+ - when finished then FPGA_tbuf_memory_remaining_nof_packets_R = 0
+ False = stop dumping packets immediately
SDPFW:
- loops over one or multiple ai
SC / dump tool:
- takes care that only one global pn is selected at a time to avoid 10GbE link overload
- - loops global pn, ai via FPGA_tbuf_dump_enable_RW and FPGA_tbuf_dumping_R
- - use FPGA_tbuf_dumping_R to see whether PN is busy dumping,
- - use FPGA_tbuf_dump_remaining_nof_packets_R = 0 to see whether PN dumping has finished
- if FPGA_tbuf_dump_enable_RW is made False before PN dumping has finished, then
- FPGA_tbuf_dump_remaining_nof_packets_R can be > 0.
-
- . FPGA_tbuf_dumping_R[pn]
- True when dump is busy,
- False when dump has finished.
- - when busy then FPGA_tbuf_read_nof_packets_R increments until it reaches initial value of
- FPGA_tbuf_dump_remaining_nof_packets_R
- - when finished then FPGA_tbuf_dump_remaining_nof_packets_R = 0
-
- . FPGA_tbuf_dump_nof_packets_R[pn][ai]
- amount of packets that will be dumped for FPGA_tbuf_dump_timestamp_range_RW,
- forced to 0 if FPGA_tbuf_dump_timestamp_range_RW is not in buffer
-
- . FPGA_tbuf_dump_remaining_nof_packets_R[pn][ai]
+ - loops global pn, ai via FPGA_tbuf_dump_enable_RW
+
+ . FPGA_tbuf_memory_remaining_nof_packets_R[pn][ai]
amount of packets that still need to be dumped,
- = 0, when FPGA_tbuf_dump_enable_RW is False,
- = dump_last_page_index_RW - dump_first_page_index_RW + 1, when FPGA_tbuf_dump_enable_RW is True.
+ starting at reg_dump_nof_pages_RW and then decrementing down to 0, when
+ FPGA_tbuf_dump_enable_RW is True. If it does not reach 0 then there is something wrong in SDPFW.
- FPGA_tbuf_read_nof_packets_R[pn][ai]
+ FPGA_tbuf_memory_read_nof_packets_R[pn][ai]
amount of packets that have been read so far
- FPGA_tbuf_read_nof_memory_errors_R[pn][ai]
- amount of packets that have been read and had a CRC error, count per ai, because each ai has own CRC
+ FPGA_tbuf_memory_dropped_nof_packets_R[pn][ai]
+ amount of packets that have been read and had a CRC error,
+ count per ai, because each ai has own CRC
- FPGA_tbuf_dumped_nof_packets_R[pn][ai]
+ FPGA_tbuf_memory_dumped_nof_packets_R[pn][ai]
amount of packets that have been dumped, packets with a read error are not passed on for dump
- = FPGA_tbuf_read_nof_packets_R - FPGA_tbuf_read_nof_memory_errors_R,
+ = FPGA_tbuf_memory_read_nof_packets_R - FPGA_tbuf_memory_dropped_nof_packets_R,
Not: FPGA_tbuf_clear_total_counts_RW[pn] --> clear all TBuf total counts in pn,
total count not needed if MP is read after every dump
Not: FPGA_tbuf_dump_enable_RW[pn] -- antenna index
Not: Fixed buffer sizes, so no need to allocate pages per ai.
+ * Ring transport:
+
* 10GbE output:
. FPGA_tbuf_output_hdr_eth_destination_mac_RW
. FPGA_tbuf_output_hdr_ip_destination_address_RW
. FPGA_tbuf_output_hdr_udp_destination_port_RW
- . FPGA_tbuf_output_enable_RW[pn]
- True : pass on dumped packets to 10GbE output
- False : stop 10GbE output
+
+ . FPGA_tbuf_output_enable_RW[pn] = reg_output_enable_RW
+ Enable output on the pn at end of ring that has interface to CEP.
+
+ * 10GbE output monitor:
+ . FPGA_tbuf_output_nof_packets_R[pn]
+ Number of dump packets that have been output while FPGA_tbuf_output_enable_RW = True,
+ reset to 0 when FPGA_tbuf_output_clear_counts_RW = True event
+ . FPGA_tbuf_output_clear_counts_RW[pn]
+ Use dp_strobe_total_count with MM clear register rather than in_clr = revt(reg_output_enable_RW) and
+ rather then dp_bsn_monitor with sync = revt(reg_output_enable_RW).
* Memory DDR4:
With streaming use of io_ddr then the dvr_wr_flush_en = '0' (so ctlr_wr_flush_en = 0 in MP), because
@@ -391,65 +409,93 @@ The CP FPGA_beamlet_output_nof_beamlets_RW is not supported in SDPTR and SDPFW y
* Memory buffer:
REG_TBUF_RAW new in node_sdp_transient_buffer_raw.vhd
- . record_all_RW
+ . reg_record_all_RW = FPGA_tbuf_reg_record_all_RW
True = record all antenna inputs,
False = record only half of the antenna inputs, the once that have even index.
- . record_enable_RW
- True = pn is recording, all ai or half of ai (dependent on record_all_RW)
+ . reg_record_enable_RW = FPGA_tbuf_record_enable_RW
+ True = pn is recording, all ai or half of ai (dependent on reg_record_all_RW)
False = pn is frozen
. c_tbuf_nof_samples_per_page = c_tbuf_nof_samples_per_packet = 2000
- . nof_ddr_words_per_page_R = 657 or 329, depends on FPGA_tbuf_record_all_RW
- SDPTR: ddr_nof_pages = floor(ddr_gigabytes * 1024**3 / (nof_ddr_words_per_page_R * ctrl_nof_bytes_per_ddr_word)
+ . reg_nof_ddr_words_per_page_R = 657 or 329, depends on reg_record_enable_RW
+ SDPTR: ddr_nof_pages = floor(ddr_gigabytes * 1024**3 / (reg_nof_ddr_words_per_page_R * ctrl_nof_bytes_per_ddr_word)
- . recorded_first_page_index_R
- freezes when recording stops by record_enable_RW = False,
- restarts at 0 when recording starts by record_enable_RW = True,
+ . reg_recorded_first_page_R
+ freezes when recording stops by reg_record_enable_RW = False,
+ restarts at 0 when recording starts by reg_record_enable_RW = True,
first page that was recorded in ddr,
remains 0 until recording has filled the circular buffer once,
- equals recorded_last_page_index + 1 when recording continues
- recorded_last_page_index_R
- freezes when recording stops by record_enable_RW = False,
- restarts at 0 when recording starts by record_enable_RW = True,
+ equals reg_recorded_last_page_R + 1 when recording continues
+ reg_recorded_last_page_R
+ freezes when recording stops by reg_record_enable_RW = False,
+ restarts at 0 when recording starts by reg_record_enable_RW = True,
last page that was recorded in ddr, increments during recording
- . recorded_first_rsn_R
- RSN of block at recorded_first_page_index
- recorded_last_rsn_R
- RSN of block at recorded_last_page_index
+ . reg_recorded_first_rsn_R
+ RSN of block at reg_recorded_first_page_R
+ reg_recorded_last_rsn_R
+ RSN of block at reg_recorded_last_page_R
+
+ . reg_dump_start_page_RW --> index of start page to dump, same for all ai in pn
+ reg_dump_start_rsn_RW --> RSN of reg_dump_start_page_RW
+ reg_dump_nof_pages_RW
+ Number of pages = packets to dump, starting at reg_dump_start_page_RW,
+ Use nof_pages instead of index of last_page, to be able to set 0 pages, same for all ai in pn
- . dump_first_page_index_RW --> index of first page to dump, same for all ai in pn
- dump_last_page_index_RW --> index of last page to dump, same for all ai in pn
SDPTR:
# Get RSN range from timestamp range
- FPGA_tbuf_dump_timestamp_range_RW / raw_sample_period --> dump_start_rsn, dump_end_rsn
+ dump_start_rsn = FPGA_tbuf_dump_start_timestamp_RW / T_adc
+ dump_end_rsn = FPGA_tbuf_dump_end_timestamp_RW / T_adc
# Determine start page that includes start RSN
- offset_page = floor((dump_start_rsn - recorded_first_rsn_R) / c_tbuf_nof_samples_per_page)
+ offset_page = floor((dump_start_rsn - reg_recorded_first_rsn_R) / c_tbuf_nof_samples_per_page)
if offset_page < 0:
offset_page = 0
- dump_start_page = recorded_first_page_index + offset_page
+ dump_start_page = reg_recorded_first_page_R + offset_page
# Determine end page that includes end RSN
- offset_page = ceil((dump_end_rsn - recorded_last_rsn_R) / c_tbuf_nof_samples_per_page)
+ offset_page = ceil((dump_end_rsn - reg_recorded_last_rsn_R) / c_tbuf_nof_samples_per_page)
if offset_page > 0:
offset_page = 0
- dump_end_page = recorded_last_page_index + offset_page
+ dump_end_page = reg_recorded_last_page_R + offset_page
dump_nof_pages = dump_end_page - dump_start_page + 1
-
- # Report nof packts that will be dumped
- FPGA_tbuf_dump_nof_packets_R = 0
if dump_nof_pages > 0:
- FPGA_tbuf_dump_nof_packets_R = dump_nof_pages
+ dump_nof_pages = 0
+
+ # Set packets that will be dumped by SDPTR
+ reg_dump_start_page_RW = dump_start_page
+ reg_dump_nof_pages_RW = dump_nof_pages
+
+ . reg_memory_read_nof_packets_R[ai]
+ amount of packets that have been read so far
+ reg_memory_read_nof_errors_R[ai]
+ amount of packets that have been read and were dropped because they had a CRC error,
+ count per ai, because each ai has own CRC
+ reg_memory_remaining_nof_packets_R[ai]
+ amount of packets that still need to be read,
+ = reg_dump_nof_pages_RW - reg_memory_read_nof_packets_R
+ reg_memory_dumped_nof_packets_R[ai]
+ amount of packets that have been read correctly and were passed on to ring
+ = reg_memory_read_nof_packets_R - reg_memory_read_nof_errors_R
+
+ FPGA_tbuf_memory_read_nof_packets_R[pn][ai] = reg_memory_read_nof_packets_R
+ FPGA_tbuf_memory_dropped_nof_packets_R[pn][ai] = reg_memory_read_nof_errors_R
+ FPGA_tbuf_memory_remaining_nof_packets_R[pn][ai] = reg_memory_remaining_nof_packets_R
+ FPGA_tbuf_memory_dumped_nof_packets_R[pn][ai] = reg_memory_dumped_nof_packets_R
+
+ FPGA_tbuf_memory_clear_counts[pn]
+ Use dp_strobe_total_count with MM clear register, rather than in_clr = revt(reg_dump_enable_RW)
+ to clear all reg_memory_* counters.
+
+ . reg_dump_enable_RW[ai]
+ True = start / keep dumping packets for the requested ai,
+ False = stop dumping packets immediately
+ When True maintain reg_memory counters, when False clear reg_memory counters to 0.
- SDPTR based on:
- . FPGA_tbuf_dump_timestamp_range_RW[pn][rsn] (start_rsn, end_rsn)
- . FPGA_tbuf_dump_enable_RW[pn][ai]
- sets:
- . dump_first_page_RW = page index of from_rsn
- . dump_nof_pages_RW = nof pages in range from_rsn, to_rsn
- . dump_antenna_input_RW = active ai in FPGA_tbuf_dump_enable_RW
- . dump_enable_RW <-- enable to dump ai,
+ . reg_output_enable_RW
+ True : pass on dumped packets from ring to 10GbE output
+ False : stop 10GbE output immediately, any packets that still arrive from the ring will
+ be discarded.
Not (no peek and poke):
. FPGA_tbuf_memory_address_RW[pn]
@@ -457,11 +503,84 @@ The CP FPGA_beamlet_output_nof_beamlets_RW is not supported in SDPTR and SDPFW y
FPGA_tbuf_memory_read_data_R[pn] --> read data results from FPGA_tbuf_memory_read_nof_words_RW
. FPGA_tbuf_memory_write_data_words_RW[pn] --> write data words (512b) to FPGA_tbuf_memory_address_RW
- Not: FPGA_tbuf_page_period_R # = raw_sample_period * 23.36 us
-
-
-6) TBuf ICD STAT/SDP-CEP
+6) SC / dump tool operation
+
+* Initialize output:
+ . write FPGA_tbuf_output_hdr_eth_destination_mac_RW
+ . write FPGA_tbuf_output_hdr_ip_destination_address_RW
+ . write FPGA_tbuf_output_hdr_udp_destination_port_RW
+
+* Enable output:
+ . write FPGA_tbuf_output_enable_RW = True for pn that has the 10GbE interface to CEP
+
+* Prepare recording:
+ . write FPGA_tbuf_reg_record_all_RW
+
+* Monitor every 1 s:
+ . read FPGA_tbuf_signal_input_rsn_R = RSN at sync : expected increment by FPGA_tbuf_signal_input_nof_samples_R
+ every 1 s when FPGA_processing_enable_RW = True, else -1
+ read FPGA_tbuf_signal_input_nof_blocks_R : expected value nof_block_per_sync = 100k or 80k
+ read FPGA_tbuf_signal_input_nof_samples_R : expected value nof_clk_per_sync = 200M or 160M
+
+* Loop:
+ * Start recording:
+ . write FPGA_tbuf_record_enable_RW = True to start recording,
+ . read FPGA_tbuf_record_enable_R to check that recording has started.
+
+ * Wait until external trigger
+
+ * Stop recording:
+ . write FPGA_tbuf_record_enable_RW = False to stop recording,
+ . read FPGA_tbuf_record_enable_R to check that recording has stopped,
+ . read FPGA_tbuf_recorded_last_timestamp_R[pn] and
+ read FPGA_tbuf_recorded_first_timestamp_R[pn] to know recorded time interval.
+
+ * Clear counts:
+ . write FPGA_tbuf_output_clear_counts_RW = True to clear FPGA_tbuf_output_nof_packets_R
+ . write FPGA_tbuf_memory_clear_counts = True to clear FPGA_tbuf_memory_*_R counts
+
+ * Prepare dump:
+ . write FPGA_tbuf_dump_start_timestamp_RW to request start time of dump interval
+ . write FPGA_tbuf_dump_end_timestamp_RW to request end time of dump interval
+ . read FPGA_tbuf_dump_start_timestamp_R to check actual start time of dump interval
+ . read FPGA_tbuf_dump_end_timestamp_R to check actual end time of dump interval
+ . read FPGA_tbuf_dump_nof_packets_R to know how many packets will be dumped per ai
+
+ * Do dump:
+ for pn in range(N_pn):
+ . write FPGA_tbuf_dump_enable_RW = True to start dumping from pn
+ . read FPGA_tbuf_dump_enable_R to wait until dumping has started in pn,
+ for enabled ai in range(A_pn):
+ . read FPGA_tbuf_memory_read_nof_packets_R[ai] == FPGA_tbuf_dump_nof_packets_R and
+ read FPGA_tbuf_memory_remaining_nof_packets_R[ai] == 0 to wait until dumping has
+ finished for all ai. If it does not finish, then timeout break because there is
+ something wrong in SDPFW.
+ for enabled ai in range(A_pn):
+ . read FPGA_tbuf_memory_dropped_nof_packets_R[ai] to monitor nof dropped packets due to memory errors
+ . read FPGA_tbuf_memory_dumped_nof_packets_R[ai] to monitor nof packets that were put on ring
+
+ In case of dump timeout:
+ . write FPGA_tbuf_dump_enable_RW = False to force stop dumping from pn
+
+ * Monitor dump results:
+ . read packet counts:
+ N_remaining = sum(FPGA_tbuf_memory_remaining_nof_packets_R[pn][ai])
+ N_read = sum(FPGA_tbuf_memory_read_nof_packets_R[pn][ai])
+ N_dropped = sum(FPGA_tbuf_memory_dropped_nof_packets_R[pn][ai])
+ N_dumped = sum(FPGA_tbuf_memory_dumped_nof_packets_R[pn][ai])
+ N_lost = N_read - N_dropped - N_dumped
+ N_output = FPGA_tbuf_output_nof_packets_R
+ . Expected results:
+ . N_remaining == 0, else something went wrong in SDPFW
+ . N_dumped = N_read - N_dropped, else something went wrong in SDPFW
+ . N_dropped == 0, else packets got lost due to DDR4 memory access errors
+ . N_lost == 0, else packets got lost on the ring
+ . N_read == FPGA_tbuf_dump_nof_packets_R * nof active ai, else something went wrong in SDPFW
+ . N_output == N_read - N_dropped - N_lost, else something went wrong in SDPFW
+
+
+7) TBuf ICD STAT/SDP-CEP
- LOFAR1:
- 16b preamble = 0xA55A --> 8b marker + 8b version_id (as in beamlet packet)
@@ -488,20 +607,24 @@ The CP FPGA_beamlet_output_nof_beamlets_RW is not supported in SDPTR and SDPFW y
. 8b version_id
- 32b observation_id --> like for beamlets, may be useful for cosmic ray piggy back, not in LOFAR1
. 16b station_info
- - 1b hba_antenna_field (HBA-0, HBA-1)
- - 15b station_id
+ - 4b antenna_field_index (e.g. HBA-0, HBA-1)
+ - 12b station_id
. 16b source_info (as in beamlet packet)
- - 3b reserved
- 1b antenna_band_index (LB, HB)
- 2b nyquist_zone_index
- 1b f_adc --> sample clock rate, period is 5 ns or 6.25 ns
+ - 3b reserved
- 4b sample_width --> 14b, where 16b is represented by 0
- 5b gn_index --> purpose fault analysis
. 32b reserved
- . 8b signal_input_index --> 0..191 ==> antenna_input_index 0..95
+ . 8b antenna_input_index --> 0..95
. 16b nof_samples_per_packet --> (8kB - 16) / 14b = 4672 (= 1022 words of 64b) --> log2() = 13b
. 64b RSN = Sample Sequence Number --> is prefered over a BSN, because RSN can start at any sample, whereas a BSN has to fit start at 1970.
+??? 4b antenna_field_index in station_info
+??? 8b gn_index
+??? 2 Byte antenne_input_index
+
- headers: 14 + 20 + 8 + 24 = 66 bytes
crc: 4 bytes
@@ -514,10 +637,12 @@ SigMF:
Tammo Jan 25 nov 2022:
-Hoi Eric, over het opslaan van complex voltage data, dat ik gisteren tijdens de group meeting even noemde: het metadataformaat heet SigMF. . Het is gewoon een json-bestandje dat je naast een databestand met alleen complex voltages opslaat. Een prima viewer hiervoor is inspectrum ( https://github.com/miek/inspectrum ). Als data formaat voor streaming complex voltages gebruiken we difi (een subset van vita49) over ZeroMQ.
+Hoi Eric, over het opslaan van complex voltage data, dat ik gisteren tijdens de group meeting even noemde: het metadataformaat heet SigMF.
+Het is gewoon een json-bestandje dat je naast een databestand met alleen complex voltages opslaat. Een prima viewer hiervoor is inspectrum
+( https://github.com/miek/inspectrum ). Als data formaat voor streaming complex voltages gebruiken we difi (een subset van vita49) over ZeroMQ.
-7) Crossbar
+8) Crossbar
* It is not possible to combine 3 * 12 * 14b = 3 * 168b = 514b into one controller word,
because it must be possible to individually record and stop signal inputs. Therefore