From 29cf2fb3d2dcd3a7854d32ff4285fef2a58bbda3 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 8 Jan 2015 13:07:45 +0000
Subject: [PATCH] Added comment about dvr interface using the
t_mem_ctlr_mosi/miso records.
---
libraries/io/ddr/src/vhdl/io_ddr.vhd | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index 80fbd7a884..353bb4ca0f 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -91,6 +91,14 @@
--
-- * = clock domain crossing between dvr_clk and ctlr_clk clock domains.
--
+-- The dvr interface is mapped also on the t_mem_ctlr_mosi/miso interface:
+-- dvr_miso.done <= dvr_done; -- Requested wr or rd sequence is done
+-- dvr_en <= dvr_mosi.burstbegin;
+-- dvr_wr_not_rd <= dvr_mosi.wr; -- No need to use dvr_mosi.rd
+-- dvr_start_address <= dvr_mosi.address(c_ctlr_address_w-1 DOWNTO 0);
+-- dvr_nof_data <= dvr_mosi.burstsize(c_ctlr_address_w-1 DOWNTO 0);
+-- dvr_wr_flush_en <= dvr_mosi.flush
+--
-- Remarks:
-- . If the dvr_clk=ctlr_clk then the clock domain crossing logic defaults
-- to wires. However dvr_clk could also be the dp_clk or the mm_clk and then
@@ -181,8 +189,8 @@ ARCHITECTURE str OF io_ddr IS
CONSTANT c_wr_fifo_af_margin : NATURAL := 4 + 1; -- use +1 to compensate for latency introduced by registering wr_siso.ready due to RL=0
CONSTANT c_rd_fifo_af_margin : NATURAL := 4 + g_tech_ddr.maxburstsize; -- use ctlr_rd_src_in.ready to only start new rd access when there is sufficient space in the read FIFO
- SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
- SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
+ SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
+ SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
SIGNAL ctlr_mosi : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst;
SIGNAL ctlr_miso : t_mem_ctlr_miso := c_mem_ctlr_miso_rst;
--
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