Use hdl_lib_include_ip to include the TSE IP for all desigs that use this unb*_board.

boards/uniboard1/libraries/unb1_board/hdllib.cfg

@@ -3,6 +3,7 @@ hdl_library_clause_name = unb1_board_lib
 hdl_lib_uses_synth = common dp diag uth ppsh i2c tr_nonbonded eth remu technology tech_pll epcs
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
+hdl_lib_include_ip = ip_stratixiv_tse_sgmii_lvds
 
 synth_files =
     src/vhdl/unb1_board_pkg.vhd

boards/uniboard2/libraries/unb2_board/hdllib.cfg

@@ -3,6 +3,7 @@ hdl_library_clause_name = unb2_board_lib
 hdl_lib_uses_synth = common dp ppsh i2c eth remu technology tech_clkbuf tech_pll tech_fractional_pll epcs fpga_sense
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10
+hdl_lib_include_ip = ip_arria10_tse_sgmii_lvds
 
 synth_files =
     src/vhdl/unb2_board_pkg.vhd

boards/uniboard2a/libraries/unb2a_board/hdllib.cfg

@@ -3,6 +3,7 @@ hdl_library_clause_name = unb2a_board_lib
 hdl_lib_uses_synth = common dp ppsh i2c eth remu technology tech_clkbuf tech_pll tech_fractional_pll epcs fpga_sense
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e3sge3
+hdl_lib_include_ip = ip_arria10_e3sge3_tse_sgmii_lvds
 
 synth_files =
     src/vhdl/unb2_board_pkg.vhd