From 2825604e5676d499a3b0a1e7a3c48a74fb0b29fd Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 28 Apr 2016 13:19:21 +0000
Subject: [PATCH] Use hdl_lib_include_ip to include the TSE IP for all desigs
 that use this unb*_board.

---
 boards/uniboard1/libraries/unb1_board/hdllib.cfg   | 1 +
 boards/uniboard2/libraries/unb2_board/hdllib.cfg   | 1 +
 boards/uniboard2a/libraries/unb2a_board/hdllib.cfg | 1 +
 3 files changed, 3 insertions(+)

diff --git a/boards/uniboard1/libraries/unb1_board/hdllib.cfg b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
index bce15bdfb3..88fe5199cb 100644
--- a/boards/uniboard1/libraries/unb1_board/hdllib.cfg
+++ b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
@@ -3,6 +3,7 @@ hdl_library_clause_name = unb1_board_lib
 hdl_lib_uses_synth = common dp diag uth ppsh i2c tr_nonbonded eth remu technology tech_pll epcs
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
+hdl_lib_include_ip = ip_stratixiv_tse_sgmii_lvds
 
 synth_files =
     src/vhdl/unb1_board_pkg.vhd
diff --git a/boards/uniboard2/libraries/unb2_board/hdllib.cfg b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
index 30ff80632c..8e2b31afa9 100644
--- a/boards/uniboard2/libraries/unb2_board/hdllib.cfg
+++ b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
@@ -3,6 +3,7 @@ hdl_library_clause_name = unb2_board_lib
 hdl_lib_uses_synth = common dp ppsh i2c eth remu technology tech_clkbuf tech_pll tech_fractional_pll epcs fpga_sense
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10
+hdl_lib_include_ip = ip_arria10_tse_sgmii_lvds
 
 synth_files =
     src/vhdl/unb2_board_pkg.vhd
diff --git a/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg b/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg
index cb14fa462f..1b94bb3bcd 100644
--- a/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg
+++ b/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg
@@ -3,6 +3,7 @@ hdl_library_clause_name = unb2a_board_lib
 hdl_lib_uses_synth = common dp ppsh i2c eth remu technology tech_clkbuf tech_pll tech_fractional_pll epcs fpga_sense
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e3sge3
+hdl_lib_include_ip = ip_arria10_e3sge3_tse_sgmii_lvds
 
 synth_files =
     src/vhdl/unb2_board_pkg.vhd
-- 
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