Improved comment.

libraries/base/dp/src/vhdl/dp_bsn_sync_interval.vhd

@@ -31,13 +31,13 @@
 --   because it then starts at any BSN, but that is not synchronous between
 --   FPGAs.
 -- * ctrl_interval_size:
---   The period of the output sync interval is programmable via
---   ctrl_interval_size. The ctrl_interval_size is the number data samples
---   per output sync interval, so an integer multiple sample periods. The
---   g_block_size is the number of data samples per block.
+--   The output sync interval is programmable via ctrl_interval_size. The
+--   ctrl_interval_size is the number data samples per output sync interval,
+--   so an integer multiple sample periods. The g_block_size is the number of
+--   data samples per block.
 --   The output sync intervals are controlled such that on average the number
---   of blocks per sync interval is nof_blk = ctrl_interval_size /g_block_size,
---   also when they are not integer dividable.
+--   of blocks per sync interval is nof_blk = ctrl_interval_size /
+--   g_block_size, also when they are not integer dividable.
 -- * ctrl_enable:
 --   The output is enabled at the ctrl_start_bsn when ctrl_enable = '1' and the
 --   output is disable after an in_sosi.eop when ctrl_enable = '0'. If the
@@ -102,7 +102,7 @@ ENTITY dp_bsn_sync_interval IS
     -- M&C
     ctrl_enable           : IN  STD_LOGIC;
     ctrl_enable_evt       : IN  STD_LOGIC;
-    ctrl_interval_size    : IN  NATURAL;  -- = number of data valid per output sync interval
+    ctrl_interval_size    : IN  NATURAL;
     ctrl_start_bsn        : IN  STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
     mon_input_current_bsn : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
     mon_input_bsn_at_sync : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
@@ -163,7 +163,7 @@ BEGIN
   END PROCESS;
 
   p_comb : PROCESS(r, ctrl_enable, ctrl_enable_evt, ctrl_interval_size, ctrl_start_bsn, in_sosi)
-    VARIABLE v : t_reg;
+    VARIABLE v      : t_reg;
     VARIABLE v_size : NATURAL;
   BEGIN
     v := r;