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Commit 12f74f7a authored by Eric Kooistra's avatar Eric Kooistra
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Added more verifications, see list in at Developments steps, in the description section.

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1 merge request!132Renamed proc_dp_verify_sync_v2() into overloaded proc_dp_verify_sync() and...
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libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_interval.vhd
+ 365
− 78
View file @ 12f74f7a
......@@ -23,19 +23,37 @@
-- Purpose: Test bench for tb_dp_bsn_sync_interval.vhd
-- Description:
-- The tb automatically TODO verifies the following cases:
-- * when enabled the out_sosi = stimuli_sosi, except for the output sync
-- * when enabled the out_sosi = in_sosi, except for the output sync
-- interval
-- * disabling the output and re-enabling the output using c_nof_repeat
-- * disabling the output and re-enabling the output using c_nof_intervals
-- * c_ctrl_start_bsn must be in the future, else output remains disabled
-- * gaps between input blocks using c_input_gap_size > 0
-- * sync intervals that have fractional number of blocks using
-- c_ctrl_interval_size
-- c_nof_samples_per_output_sync
-- * output sync interval in case of lost input blocks
-- Usage:
-- > as 8
-- > run -all
-- View in wave window u_dut: r, nxt_r, and tb: stimuli_sosi, out_sosi,
-- View in Wave window u_dut: r, nxt_r, and tb: in_sosi, out_sosi,
-- out_sync, out_start
--
-- Development steps:
-- 1a Draft design description of dp_bsn_sync_interval
-- b Initial implementation that compiles
-- 2a Initial tb using u_stimuli to generate in_sosi and using p_stimuli
-- to test basic functionality, i.e. to get out_sosi when ctrl_enable is on
-- and no output when off.
-- b Verify that c_input_gap_size > 0 also works
-- c Add verification of out_sosi = in sosi when enabled (proc_dp_verify_sosi_equal)
-- d Add verification of out_sosi (p_verify_out_enable)
-- e Add verification of out_start and first out_sync (p_verify_out_start)
-- f Add verification of out_sosi.sync using proc_dp_verify_sync() for
-- fractional sync intervals
-- g Add verification of mon_output_sync_bsn (p_verify_mon_output_sync_bsn)
-- 3a For all ASSERTs, verify that the ERROR or FAILURE can occur by e.g.
-- temporarily changing the condition
-- b Initialy used LOOP in p_stimuli to repeat test. Later used list of
-- intervals and tb_state to try different stimuli.
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
......@@ -50,53 +68,122 @@ END tb_dp_bsn_sync_interval;
ARCHITECTURE tb OF tb_dp_bsn_sync_interval IS
CONSTANT c_clk_period : TIME := 10 ns;
CONSTANT c_bsn_w : NATURAL := 31;
CONSTANT c_dut_latency : NATURAL := 1;
CONSTANT c_nof_repeat : NATURAL := 2;
CONSTANT c_nof_block_per_input_sync : NATURAL := 9;
CONSTANT c_nof_data_per_block : NATURAL := 10;
CONSTANT c_input_gap_size : NATURAL := 3;
CONSTANT c_nof_clk_per_block : NATURAL := c_nof_data_per_block + c_input_gap_size;
CONSTANT c_nof_input_sync : NATURAL := 6;
CONSTANT c_nof_block_per_repeat : NATURAL := c_nof_block_per_input_sync * c_nof_input_sync;
CONSTANT c_nof_clk_per_repeat : NATURAL := c_nof_clk_per_block * c_nof_block_per_repeat;
CONSTANT c_enable_hi_evt : NATURAL := c_nof_clk_per_block * 4;
CONSTANT c_enable_lo_evt : NATURAL := c_nof_clk_per_repeat - (c_nof_clk_per_block * 3);
CONSTANT c_sim_nof_blocks : NATURAL := c_nof_block_per_repeat * c_nof_repeat;
CONSTANT c_clk_period : TIME := 10 ns;
CONSTANT c_bsn_w : NATURAL := 31;
CONSTANT c_dut_latency : NATURAL := 1;
--CONSTANT c_ctrl_interval_size : NATURAL := c_nof_data_per_block * 4;
CONSTANT c_ctrl_interval_size : NATURAL := c_nof_data_per_block * 9 / 2;
-- Input sync period
CONSTANT c_block_size : NATURAL := 10;
CONSTANT c_nof_block_per_input_sync : NATURAL := 17;
SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC := '1';
SIGNAL cnt : INTEGER := 0;
SIGNAL repeat : INTEGER := 0;
SIGNAL tb_end : STD_LOGIC := '0';
-- Test intervals
CONSTANT c_nof_intervals : NATURAL := 4; -- should be large enough for p_stimuli
CONSTANT c_nof_input_sync : NATURAL := 10;
CONSTANT c_nof_block_per_interval : NATURAL := c_nof_block_per_input_sync * c_nof_input_sync;
CONSTANT c_input_gap_size : NATURAL := 3;
CONSTANT c_nof_clk_per_block : NATURAL := c_block_size + c_input_gap_size;
CONSTANT c_nof_clk_per_interval : NATURAL := c_nof_clk_per_block * c_nof_block_per_interval;
CONSTANT c_start_of_interval : NATURAL := 0 + c_nof_clk_per_block * 4; -- just after start
CONSTANT c_early_in_interval : NATURAL := c_nof_clk_per_interval / 3;
CONSTANT c_mid_of_interval : NATURAL := c_nof_clk_per_interval / 2;
CONSTANT c_end_of_interval : NATURAL := c_nof_clk_per_interval - c_nof_clk_per_block * 3; -- just before end
CONSTANT c_sim_nof_blocks : NATURAL := c_nof_block_per_interval * c_nof_intervals;
CONSTANT c_nof_lost_input : NATURAL := c_nof_block_per_input_sync * 4 + 3;
-- Output sync period
--CONSTANT c_nof_samples_per_output_sync : NATURAL := c_block_size * 4;
CONSTANT c_nof_samples_per_output_sync : NATURAL := c_block_size * 9 / 2;
SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC := '1';
SIGNAL cnt : INTEGER := 0;
SIGNAL interval : INTEGER := 0;
SIGNAL tb_end : STD_LOGIC := '0';
TYPE t_stimuli_state_enum IS ( -- use short names to ease unzoomed view in Wave window
e_dis, -- disable
e_en, -- enable
e_re, -- re-enable
e_lost, -- lost input blocks
e_old -- start bsn in passed
);
SIGNAL stimuli_state : t_stimuli_state_enum := e_dis; -- to show what tb does in Wave window
-- Stimuli
SIGNAL ctrl_enable : STD_LOGIC := '0';
SIGNAL ctrl_enable_evt : STD_LOGIC := '0';
SIGNAL ctrl_interval_size : NATURAL := c_ctrl_interval_size;
SIGNAL ctrl_start_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL mon_current_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL mon_bsn_at_sync : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL mon_output_enable : STD_LOGIC;
SIGNAL mon_output_sync_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL stimuli_end : STD_LOGIC;
SIGNAL stimuli_sosi : t_dp_sosi;
SIGNAL stimuli_sync : STD_LOGIC; -- declared next to stimuli_sosi and out_sync for easier comparison in wave window
SIGNAL ctrl_enable : STD_LOGIC := '0';
SIGNAL ctrl_enable_evt : STD_LOGIC := '0';
SIGNAL ctrl_interval_size : NATURAL := c_nof_samples_per_output_sync;
SIGNAL ctrl_start_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL mon_input_current_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL mon_input_bsn_at_sync : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL mon_output_enable : STD_LOGIC;
SIGNAL mon_output_sync_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL stimuli_sosi : t_dp_sosi := c_dp_sosi_init;
SIGNAL stimuli_sync : STD_LOGIC; -- declared next to stimuli_sosi and out_sync for easier comparison in Wave window
-- Input stimuli
SIGNAL in_lost : STD_LOGIC := '0';
SIGNAL in_sosi : t_dp_sosi := c_dp_sosi_init; -- = stimuli_sosi, with option for lost blocks
SIGNAL in_sync : STD_LOGIC;
-- Output
SIGNAL out_sync : STD_LOGIC; -- declared next to in_sync, out_start and out_sosi for easier comparison in wave window
SIGNAL out_start : STD_LOGIC;
SIGNAL out_sosi : t_dp_sosi;
SIGNAL out_sync : STD_LOGIC; -- declared next to in_sync, out_start and out_sosi for easier comparison in Wave window
SIGNAL out_start : STD_LOGIC;
SIGNAL out_enable : STD_LOGIC;
SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init;
-- Verify
SIGNAL in_sosi_integer : t_dp_sosi_integer;
SIGNAL out_sosi_integer : t_dp_sosi_integer;
SIGNAL verify_sosi_equal : STD_LOGIC := '0';
SIGNAL verify_sync : STD_LOGIC := '1';
SIGNAL prev_out_enable : STD_LOGIC := '0';
SIGNAL out_eop_dly : STD_LOGIC := '0';
SIGNAL pending_out_enable : STD_LOGIC := '0';
SIGNAL pending_out_disable : STD_LOGIC := '0';
SIGNAL expected_out_enable : STD_LOGIC := '0';
SIGNAL expecting_out_start : STD_LOGIC := '0';
SIGNAL dbg_nof_blk : NATURAL := 0;
SIGNAL dbg_extra : NATURAL := 0;
SIGNAL dbg_expected_bsn : NATURAL := 0;
PROCEDURE proc_output_enable(SIGNAL clk : IN STD_LOGIC;
SIGNAL cnt : IN INTEGER;
SIGNAL mon_input_bsn_at_sync : IN STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL stimuli_state : OUT t_stimuli_state_enum;
SIGNAL ctrl_start_bsn : OUT STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL ctrl_enable : OUT STD_LOGIC;
SIGNAL ctrl_enable_evt : OUT STD_LOGIC) IS
BEGIN
stimuli_state <= e_en;
ctrl_start_bsn <= ADD_UVEC(mon_input_bsn_at_sync, TO_UVEC(c_nof_block_per_input_sync, c_natural_w)); -- determine BSN in the future
ctrl_enable <= '1';
ctrl_enable_evt <= '1';
proc_common_wait_some_cycles(clk, 1);
ctrl_enable_evt <= '0';
END proc_output_enable;
PROCEDURE proc_output_re_enable(SIGNAL clk : IN STD_LOGIC;
SIGNAL cnt : IN INTEGER;
SIGNAL mon_input_bsn_at_sync : IN STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL stimuli_state : OUT t_stimuli_state_enum;
SIGNAL ctrl_start_bsn : OUT STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL ctrl_enable : OUT STD_LOGIC;
SIGNAL ctrl_enable_evt : OUT STD_LOGIC) IS
BEGIN
proc_output_enable(clk, cnt, mon_input_bsn_at_sync, stimuli_state, ctrl_start_bsn, ctrl_enable, ctrl_enable_evt);
stimuli_state <= e_re;
END proc_output_re_enable;
PROCEDURE proc_output_disable(SIGNAL stimuli_state : OUT t_stimuli_state_enum;
SIGNAL ctrl_enable : OUT STD_LOGIC) IS
BEGIN
stimuli_state <= e_dis;
ctrl_enable <= '0';
END proc_output_disable;
BEGIN
......@@ -113,22 +200,63 @@ BEGIN
p_stimuli : PROCESS
BEGIN
stimuli_state <= e_dis;
proc_common_wait_until_low(clk, rst);
FOR rep IN 0 TO c_nof_repeat-1 LOOP
-- Enable output
proc_common_wait_until_value(rep * c_nof_clk_per_repeat + c_enable_hi_evt, clk, cnt);
ctrl_start_bsn <= ADD_UVEC(mon_bsn_at_sync, TO_UVEC(c_nof_block_per_input_sync, c_natural_w)); -- determine BSN in the future
ctrl_enable <= '1';
ctrl_enable_evt <= '1';
------------------------------------------------------------------------------
-- Enable and disable output
------------------------------------------------------------------------------
interval <= 0; proc_common_wait_some_cycles(clk, 1);
proc_common_wait_until_value(interval * c_nof_clk_per_interval + c_start_of_interval, clk, cnt);
-- Start of interval: Enable output
proc_output_enable(clk, cnt, mon_input_bsn_at_sync, stimuli_state, ctrl_start_bsn, ctrl_enable, ctrl_enable_evt);
-- End of interval: Disable output
proc_common_wait_until_value(interval * c_nof_clk_per_interval + c_end_of_interval, clk, cnt);
proc_output_disable(stimuli_state, ctrl_enable);
------------------------------------------------------------------------------
-- Re enable output when already enabled
------------------------------------------------------------------------------
interval <= interval + 1; proc_common_wait_some_cycles(clk, 1);
-- Start of interval: Enable output
proc_common_wait_until_value(interval * c_nof_clk_per_interval + c_start_of_interval, clk, cnt);
proc_output_enable(clk, cnt, mon_input_bsn_at_sync, stimuli_state, ctrl_start_bsn, ctrl_enable, ctrl_enable_evt);
-- Mid of interval: Re-enable output
proc_common_wait_until_value(interval * c_nof_clk_per_interval + c_mid_of_interval, clk, cnt);
proc_output_re_enable(clk, cnt, mon_input_bsn_at_sync, stimuli_state, ctrl_start_bsn, ctrl_enable, ctrl_enable_evt);
-- End of interval: Disable output
proc_common_wait_until_value(interval * c_nof_clk_per_interval + c_end_of_interval, clk, cnt);
proc_output_disable(stimuli_state, ctrl_enable);
------------------------------------------------------------------------------
-- Lost input blocks
------------------------------------------------------------------------------
interval <= interval + 1; proc_common_wait_some_cycles(clk, 1);
-- Start of interval: Enable output
proc_common_wait_until_value(interval * c_nof_clk_per_interval + c_start_of_interval, clk, cnt);
proc_output_enable(clk, cnt, mon_input_bsn_at_sync, stimuli_state, ctrl_start_bsn, ctrl_enable, ctrl_enable_evt);
-- Early in interval: Disable input to simulate lost blocks
proc_common_wait_until_value(interval * c_nof_clk_per_interval + c_early_in_interval, clk, cnt);
stimuli_state <= e_lost;
proc_common_wait_until_high(clk, stimuli_sosi.eop);
in_lost <= '1'; -- high after eop, so high at next sop
FOR I IN 0 TO c_nof_lost_input-1 LOOP
proc_common_wait_some_cycles(clk, 1);
ctrl_enable_evt <= '0';
-- Disable output
proc_common_wait_until_value(rep * c_nof_clk_per_repeat + c_enable_lo_evt, clk, cnt);
ctrl_enable <= '0';
repeat <= repeat + 1;
proc_common_wait_until_high(clk, stimuli_sosi.eop);
END LOOP;
in_lost <= '0'; -- low after eop, so low at next sop
stimuli_state <= e_en;
-- End of interval: Disable output
proc_common_wait_until_value(interval * c_nof_clk_per_interval + c_end_of_interval, clk, cnt);
proc_output_disable(stimuli_state, ctrl_enable);
WAIT;
END PROCESS;
......@@ -138,11 +266,11 @@ BEGIN
GENERIC MAP (
g_sync_period => c_nof_block_per_input_sync,
g_err_init => 0,
g_err_incr => 0, -- do not increment, to not distract from viewing of BSN in wave window
g_err_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
g_channel_init => 0,
g_channel_incr => 0, -- do not increment, to not distract from viewing of BSN in wave window
g_channel_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
g_nof_repeat => c_sim_nof_blocks,
g_pkt_len => c_nof_data_per_block,
g_pkt_len => c_block_size,
g_pkt_gap => c_input_gap_size
)
PORT MAP (
......@@ -153,18 +281,176 @@ BEGIN
src_out => stimuli_sosi,
-- End of stimuli
tb_end => stimuli_end
tb_end => tb_end
);
-- Input with option to loose data blocks
p_in_sosi : PROCESS(stimuli_sosi, in_lost)
BEGIN
in_sosi <= stimuli_sosi;
IF in_lost = '1' THEN
in_sosi.sync <= '0';
in_sosi.sop <= '0';
in_sosi.eop <= '0';
in_sosi.valid <= '0';
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Verification
-----------------------------------------------------------------------------
stimuli_sync <= stimuli_sosi.sync; -- separate signal for easier viewing in wave window
out_sync <= out_sosi.sync; -- separate signal for easier viewing in wave window
-- separate signal for easier viewing in Wave window
stimuli_sync <= stimuli_sosi.sync;
in_sync <= in_sosi.sync;
out_sync <= out_sosi.sync;
-----------------------------------------------------------------------------
-- . Verify out_enable
-----------------------------------------------------------------------------
out_eop_dly <= out_sosi.eop WHEN rising_edge(clk);
p_expected_out_enable : PROCESS(ctrl_enable, ctrl_enable_evt, in_sosi, ctrl_start_bsn, pending_out_enable, pending_out_disable, out_eop_dly)
BEGIN
-- Determine expected out_enable
IF ctrl_enable = '1' THEN
-- Detect output enable event and determine whether it is scheduled in the future
IF ctrl_enable_evt = '1' THEN
IF UNSIGNED(in_sosi.bsn) < UNSIGNED(ctrl_start_bsn) THEN
pending_out_enable <= '1';
END IF;
END IF;
-- Expected out_enable enabled
IF pending_out_enable = '1' THEN
IF UNSIGNED(in_sosi.bsn) >= UNSIGNED(ctrl_start_bsn) THEN
expected_out_enable <= '1';
pending_out_enable <= '0';
END IF;
END IF;
-- Remove any pending output disable
pending_out_disable <= '0';
ELSE
-- Remove any pending output enable
pending_out_enable <= '0';
-- Detect output disable event
IF ctrl_enable_evt = '1' THEN
pending_out_disable <= '1';
END IF;
-- Expected out_enable disabled
IF pending_out_disable <= '1' AND out_eop_dly = '1' THEN
expected_out_enable <= '0';
pending_out_disable <= '0';
END IF;
END IF;
END PROCESS;
p_verify_out_enable : PROCESS(clk)
BEGIN
-- Use registered values to compare, to avoid combinatorial differences
-- that can occur during a simulation delta cycle. These combinatorial
-- differences are not relevant, because they get resolved after a few
-- delta cycles.
IF rising_edge(clk) THEN
IF out_enable /= expected_out_enable THEN
IF out_enable = '1' THEN
REPORT "Unexpected enabled out_enable" SEVERITY ERROR;
ELSE
REPORT "Unexpected disabled out_enable" SEVERITY ERROR;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- . Verify out_enable
-----------------------------------------------------------------------------
p_expecting_out_start : PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN
IF ctrl_enable = '1' AND ctrl_enable_evt = '1' THEN
expecting_out_start <= '1';
ELSIF out_start = '1' THEN
expecting_out_start <= '0';
END IF;
END IF;
END PROCESS;
prev_out_enable <= out_enable WHEN rising_edge(clk);
p_verify_out_start : PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN
-- Check that out_sync is active at out_start
IF out_start = '1' THEN
IF out_sync = '0' THEN
REPORT "Missing out_sync at out_start" SEVERITY ERROR;
END IF;
END IF;
-- Check unexpected out_start
IF out_start = '1' AND expecting_out_start = '0' THEN
REPORT "Unexpected out_start" SEVERITY ERROR;
END IF;
-- Check when out_enable goes low whether out_start was missed
IF out_enable = '0' AND prev_out_enable = '1' THEN
IF expecting_out_start = '1' THEN
REPORT "Missed out_start" SEVERITY ERROR;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- . Verify out_sosi = in_sosi, for all fields except out_sosi.sync
-----------------------------------------------------------------------------
-- Use registered values for func_dp_stream_slv_to_integer(), to avoid
-- Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 at
-- Time: 0 fs in Transcript window. Using only c_dp_sosi_init at signal
-- declaration is not sufficient.
verify_sosi_equal <= out_enable WHEN rising_edge(clk);
in_sosi_integer <= func_dp_stream_slv_to_integer(in_sosi, c_natural_w) WHEN rising_edge(clk);
out_sosi_integer <= func_dp_stream_slv_to_integer(out_sosi, c_natural_w) WHEN rising_edge(clk);
proc_dp_verify_sosi_equal( "bsn", clk, verify_sosi_equal, out_sosi_integer, in_sosi_integer);
proc_dp_verify_sosi_equal( "sop", clk, verify_sosi_equal, out_sosi_integer, in_sosi_integer);
proc_dp_verify_sosi_equal( "eop", clk, verify_sosi_equal, out_sosi_integer, in_sosi_integer);
proc_dp_verify_sosi_equal("valid", clk, verify_sosi_equal, out_sosi_integer, in_sosi_integer);
proc_dp_verify_sosi_equal( "data", clk, verify_sosi_equal, out_sosi_integer, in_sosi_integer);
-----------------------------------------------------------------------------
-- . Verify out_sosi.sync interval
-----------------------------------------------------------------------------
proc_dp_verify_sync(TO_UINT(ctrl_start_bsn),
ctrl_interval_size,
c_block_size, clk,
out_enable,
out_sosi.sync,
out_sosi.sop,
out_sosi.bsn,
dbg_nof_blk,
dbg_extra,
dbg_expected_bsn);
-----------------------------------------------------------------------------
-- . Verify mon_output_sync_bsn
-----------------------------------------------------------------------------
p_verify_mon_output_sync_bsn : PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN
IF out_sosi.sync = '1' THEN
--ASSERT UNSIGNED(mon_output_sync_bsn) = UNSIGNED(out_sosi.bsn) REPORT "Wrong mon_output_sync_bsn" SEVERITY ERROR;
END IF;
END IF;
END PROCESS;
tb_end <= stimuli_end;
-----------------------------------------------------------------------------
-- DUT: dp_bsn_sync_interval
......@@ -172,28 +458,29 @@ BEGIN
dut : ENTITY work.dp_bsn_sync_interval
GENERIC MAP (
g_bsn_w => c_bsn_w,
g_block_size => c_nof_data_per_block,
g_pipeline => 0
g_bsn_w => c_bsn_w,
g_block_size => c_block_size,
g_pipeline => 0
)
PORT MAP (
rst => rst,
clk => clk,
rst => rst,
clk => clk,
-- M&C
ctrl_enable => ctrl_enable,
ctrl_enable_evt => ctrl_enable_evt,
ctrl_interval_size => ctrl_interval_size,
ctrl_start_bsn => ctrl_start_bsn,
mon_current_bsn => mon_current_bsn,
mon_bsn_at_sync => mon_bsn_at_sync,
mon_output_enable => mon_output_enable,
mon_output_sync_bsn => mon_output_sync_bsn,
ctrl_enable => ctrl_enable,
ctrl_enable_evt => ctrl_enable_evt,
ctrl_interval_size => ctrl_interval_size,
ctrl_start_bsn => ctrl_start_bsn,
mon_input_current_bsn => mon_input_current_bsn,
mon_input_bsn_at_sync => mon_input_bsn_at_sync,
mon_output_enable => mon_output_enable,
mon_output_sync_bsn => mon_output_sync_bsn,
-- Streaming
in_sosi => stimuli_sosi,
out_sosi => out_sosi,
out_start => out_start
in_sosi => in_sosi,
out_sosi => out_sosi,
out_start => out_start,
out_enable => out_enable
);
END tb;
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