more modelsim error fixes

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl

@@ -30,6 +30,7 @@
 
 vmap  altera_iopll_180           ./work/
 
+
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
   vlog  "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk25_altera_iopll_180_fp6fpla.vo"  -work altera_iopll_180         
 
@@ -39,5 +40,14 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
   vlog  "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_180_qkytlfy.vo" -work altera_iopll_180          
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll/sim"
-  vlog  "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.vo" -work altera_iopll_180          
+# # Refreshing /home/hiemstra/git/hdl/build/unb2b/modelsim/ip_arria10_e1sg_jesd204b/work.ip_arria10_e1sg_jesd204b_rx_core_pll_200mhz(rtl)
+# Loading ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_rx_core_pll_200mhz(rtl)
+# Refreshing /home/hiemstra/git/hdl/build/unb2b/modelsim/ip_arria10_e1sg_altera_iopll_180/work.ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz_altera_iopll_180_4sgpama
+# Loading altera_iopll_180.ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz_altera_iopll_180_4sgpama
+# Loading altera_lnsim_ver.altera_iopll
+# ** Error (suppressible): (vsim-3584) /home/hiemstra/git/hdl/build/unb2b/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/sim/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz_altera_iopll_180_4sgpama.vo(155): Module parameter 'prot_mode' not found for override.
+#    Time: 0 fs  Iteration: 0  Instance: /tb_tech_jesd204b/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_corepll_freqsel/u_ip_arria10_e1sg_jesd204b_rx_corepll_200MHz/iopll_0 File: /home/hiemstra/git/hdl/build/unb2b/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/sim/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz_altera_iopll_180_4sgpama.vo
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/sim"
+  vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz_altera_iopll_180_4sgpama.vo" -work altera_iopll_180          
+

libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl

@@ -98,8 +98,8 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_k23srea.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
 
 # jesd204b rx
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx/sim"
-  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_jesd204b_rx_altera_xcvr_native_a10_180_vcpx3ja.sv"      -L altera_common_sv_packages -work altera_xcvr_native_a10_180            
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_jesd204b_rx_200MHz_altera_xcvr_native_a10_180_vcpx3ja.sv"      -L altera_common_sv_packages -work altera_xcvr_native_a10_180            
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_vcpx3ja.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_180  
 
 # jesd204b tx