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Commit 256e59bb authored by Eric Kooistra's avatar Eric Kooistra
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Removed transceiver_pll_156_312/. Now use pll_xgmii_mac_clocks/ instead.

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libraries/technology/ip_arria10/transceiver_pll_156_312/hdllib.cfg deleted 100644 → 0
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hdl_lib_name = ip_arria10_transceiver_pll_156_312
hdl_library_clause_name = ip_arria10_transceiver_pll_156_312_lib
hdl_lib_uses = ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
ip_arria10_transceiver_pll_156_312_top.vhd
test_bench_files =
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
libraries/technology/ip_arria10/transceiver_pll_156_312/ip/compile_ip.tcl deleted 100644 → 0
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#------------------------------------------------------------------------------
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_pll_156_312/ip/generated/sim"
vlib ./work/
vmap ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140 ./work/
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/twentynm_xcvr_avmm.sv" -work ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/mentor/twentynm_xcvr_avmm.sv" -work ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/alt_xcvr_resync.sv" -work ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/altera_xcvr_fpll_a10.sv" -work ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/mentor/altera_xcvr_fpll_a10.sv" -work ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/a10_avmm_h.sv" -work ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/mentor/a10_avmm_h.sv" -work ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/mentor/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/alt_xcvr_pll_embedded_debug.sv" -work ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/alt_xcvr_pll_avmm_csr.sv" -work ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
vcom "$IP_DIR/ip_arria10_transceiver_pll_156_312.vhd"
libraries/technology/ip_arria10/transceiver_pll_156_312/ip/generate_ip.sh deleted 100755 → 0
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#!/bin/bash
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# -------------------------------------------------------------------------- #
#
# Purpose: Generate IP with Qsys
# Description:
# Generate the IP in a separate generated/ subdirectory.
#
# Usage:
#
# ./generate_ip.sh
#
# Tool settings for selected target "unb2" with arria10
. ${RADIOHDL}/tools/quartus/set_quartus unb2
#qsys-generate --help
# Only generate the source IP
# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
qsys-generate ip_arria10_transceiver_pll_156_312.qsys \
--synthesis=VHDL \
--simulation=VHDL \
--output-directory=generated \
--allow-mixed-language-simulation
libraries/technology/ip_arria10/transceiver_pll_156_312/ip/hdllib.cfg deleted 100644 → 0
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hdl_lib_name = ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
hdl_library_clause_name = ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140
hdl_lib_uses =
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_156_312/ip/compile_ip.tcl
synth_files =
test_bench_files =
quartus_qip_files =
generated/ip_arria10_transceiver_pll_156_312.qip
libraries/technology/ip_arria10/transceiver_pll_156_312/ip/ip_arria10_transceiver_pll_156_312.qsys deleted 100644 → 0
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<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
}
element xcvr_fpll_a10_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115R2F40I2LG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="pll_refclk0"
internal="xcvr_fpll_a10_0.pll_refclk0"
type="clock"
dir="end">
<port name="pll_refclk0" internal="pll_refclk0" />
</interface>
<interface
name="pll_powerdown"
internal="xcvr_fpll_a10_0.pll_powerdown"
type="conduit"
dir="end">
<port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
name="pll_locked"
internal="xcvr_fpll_a10_0.pll_locked"
type="conduit"
dir="end">
<port name="pll_locked" internal="pll_locked" />
</interface>
<interface
name="outclk0"
internal="xcvr_fpll_a10_0.outclk0"
type="clock"
dir="start">
<port name="outclk0" internal="outclk0" />
</interface>
<interface
name="pll_cal_busy"
internal="xcvr_fpll_a10_0.pll_cal_busy"
type="conduit"
dir="end">
<port name="pll_cal_busy" internal="pll_cal_busy" />
</interface>
<interface
name="outclk1"
internal="xcvr_fpll_a10_0.outclk1"
type="clock"
dir="start">
<port name="outclk1" internal="outclk1" />
</interface>
<module
kind="altera_xcvr_fpll_a10"
version="14.0"
enabled="1"
name="xcvr_fpll_a10_0"
autoexport="1">
<parameter name="rcfg_debug" value="0" />
<parameter name="enable_pll_reconfig" value="0" />
<parameter name="rcfg_jtag_enable" value="0" />
<parameter name="set_embedded_debug_enable" value="0" />
<parameter name="set_capability_reg_enable" value="0" />
<parameter name="set_user_identifier" value="0" />
<parameter name="set_csr_soft_logic_enable" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_fpll_a10</parameter>
<parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_h_file_enable" value="0" />
<parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_multi_enable" value="0" />
<parameter name="rcfg_profile_cnt" value="2" />
<parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_param_vals1" value="" />
<parameter name="rcfg_param_vals2" value="" />
<parameter name="system_info_device_family" value="Arria 10" />
<parameter name="gui_device_speed_grade" value="fastest" />
<parameter name="gui_fpll_mode" value="0" />
<parameter name="gui_hssi_prot_mode" value="0" />
<parameter name="gui_refclk_switch" value="false" />
<parameter name="gui_refclk1_frequency" value="100.0" />
<parameter name="gui_switchover_mode">Automatic Switchover</parameter>
<parameter name="gui_switchover_delay" value="0" />
<parameter name="gui_enable_active_clk" value="false" />
<parameter name="gui_enable_clk_bad" value="false" />
<parameter name="generate_docs" value="1" />
<parameter name="generate_add_hdl_instance_example" value="0" />
<parameter name="gui_bw_sel" value="low" />
<parameter name="gui_self_reset_enabled" value="false" />
<parameter name="silicon_rev" value="false" />
<parameter name="gui_reference_clock_frequency" value="644.53125" />
<parameter name="gui_desired_refclk_frequency" value="100.0" />
<parameter name="gui_actual_refclk_frequency" value="100.0" />
<parameter name="gui_operation_mode" value="0" />
<parameter name="gui_iqtxrxclk_outclk_index" value="0" />
<parameter name="gui_refclk_cnt" value="1" />
<parameter name="gui_refclk_index" value="0" />
<parameter name="gui_enable_fractional" value="false" />
<parameter name="gui_enable_pld_cal_busy_port" value="1" />
<parameter name="gui_enable_hip_cal_done_port" value="0" />
<parameter name="gui_hip_cal_en" value="0" />
<parameter name="gui_enable_cascade_out" value="false" />
<parameter name="gui_cascade_outclk_index" value="0" />
<parameter name="gui_enable_dps" value="false" />
<parameter name="gui_enable_manual_config" value="false" />
<parameter name="gui_hssi_output_clock_frequency" value="1250.0" />
<parameter name="gui_pll_m_counter" value="1" />
<parameter name="gui_pll_n_counter" value="1" />
<parameter name="gui_fractional_x" value="32" />
<parameter name="gui_pll_dsm_fractional_division" value="1" />
<parameter name="gui_pll_c_counter_0" value="1" />
<parameter name="gui_pll_c_counter_1" value="1" />
<parameter name="gui_pll_c_counter_2" value="1" />
<parameter name="gui_pll_c_counter_3" value="1" />
<parameter name="gui_number_of_output_clocks" value="2" />
<parameter name="gui_desired_outclk0_frequency" value="156.25" />
<parameter name="gui_actual_outclk0_frequency" value="100.0" />
<parameter name="gui_outclk0_phase_shift_unit" value="0" />
<parameter name="gui_outclk0_desired_phase_shift" value="0.0" />
<parameter name="gui_outclk0_actual_phase_shift" value="0.0" />
<parameter name="gui_outclk0_actual_phase_shift_deg" value="0.0" />
<parameter name="gui_desired_outclk1_frequency" value="312.5" />
<parameter name="gui_actual_outclk1_frequency" value="100.0" />
<parameter name="gui_outclk1_phase_shift_unit" value="0" />
<parameter name="gui_outclk1_desired_phase_shift" value="0" />
<parameter name="gui_outclk1_actual_phase_shift" value="0.0" />
<parameter name="gui_outclk1_actual_phase_shift_deg" value="0.0" />
<parameter name="gui_desired_outclk2_frequency" value="100.0" />
<parameter name="gui_actual_outclk2_frequency" value="100.0" />
<parameter name="gui_outclk2_phase_shift_unit" value="0" />
<parameter name="gui_outclk2_desired_phase_shift" value="0" />
<parameter name="gui_outclk2_actual_phase_shift" value="0 ps" />
<parameter name="gui_outclk2_actual_phase_shift_deg" value="0 deg" />
<parameter name="gui_desired_outclk3_frequency" value="100.0" />
<parameter name="gui_actual_outclk3_frequency" value="100.0" />
<parameter name="gui_outclk3_phase_shift_unit" value="0" />
<parameter name="gui_outclk3_desired_phase_shift" value="0" />
<parameter name="gui_outclk3_actual_phase_shift" value="0.0" />
<parameter name="gui_outclk3_actual_phase_shift_deg" value="0.0" />
<parameter name="gui_desired_hssi_cascade_frequency" value="100.0" />
<parameter name="enable_mcgb" value="0" />
<parameter name="mcgb_div" value="1" />
<parameter name="enable_hfreq_clk" value="0" />
<parameter name="enable_mcgb_pcie_clksw" value="0" />
<parameter name="mcgb_aux_clkin_cnt" value="0" />
<parameter name="enable_bonding_clks" value="0" />
<parameter name="enable_fb_comp_bonding" value="0" />
<parameter name="pma_width" value="64" />
<parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
<parameter name="AUTO_PLL_REFCLK0_CLOCK_RATE" value="0" />
<parameter name="AUTO_PLL_REFCLK1_CLOCK_RATE" value="-1" />
<parameter name="AUTO_PLL_REFCLK2_CLOCK_RATE" value="-1" />
<parameter name="AUTO_PLL_REFCLK3_CLOCK_RATE" value="-1" />
<parameter name="AUTO_PLL_REFCLK4_CLOCK_RATE" value="-1" />
<parameter name="AUTO_RECONFIG_CLK0_CLOCK_RATE" value="-1" />
<parameter name="AUTO_RECONFIG_CLK1_CLOCK_RATE" value="-1" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
</system>
libraries/technology/ip_arria10/transceiver_pll_156_312/ip_arria10_transceiver_pll_156_312_top.vhd deleted 100644 → 0
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-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Wrapper for generated ip_arria10_transceiver_pll_156_312.vhd
-- Description:
-- This wrapper avoids the need to vmap the ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140 library
-- in the technology independent library that instantiate this IP.
-- Remarks:
-- . Manually created from generated ip_arria10_transceiver_pll_156_312.vhd.
library IEEE;
use IEEE.std_logic_1164.all;
library ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140;
entity ip_arria10_transceiver_pll_156_312_top is
port (
pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
pll_locked : out std_logic; -- pll_locked.pll_locked
outclk0 : out std_logic; -- outclk0.clk
pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
outclk1 : out std_logic -- outclk1.clk
);
end ip_arria10_transceiver_pll_156_312_top;
architecture str of ip_arria10_transceiver_pll_156_312_top is
begin
u_ip_arria10_transceiver_pll_156_312 : entity ip_arria10_transceiver_pll_156_312_altera_xcvr_fpll_a10_140.ip_arria10_transceiver_pll_156_312
port map (
pll_refclk0 => pll_refclk0 , -- pll_refclk0.clk
pll_powerdown => pll_powerdown, -- pll_powerdown.pll_powerdown
pll_locked => pll_locked , -- pll_locked.pll_locked
outclk0 => outclk0 , -- outclk0.clk
pll_cal_busy => pll_cal_busy , -- pll_cal_busy.pll_cal_busy
outclk1 => outclk1 -- outclk1.clk
);
end str;
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