Created hdllib.cfg for generate, sim and synth of ip_arria10_pll_xgmii_mac_clocks.

libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl

+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generated/sim"
+
+vlib ./work/
+
+vmap ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140 ./work/
+
+vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/twentynm_xcvr_avmm.sv"                 -work ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/mentor/twentynm_xcvr_avmm.sv"          -work ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/alt_xcvr_resync.sv"                    -work ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/mentor/alt_xcvr_resync.sv"             -work ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/altera_xcvr_fpll_a10.sv"               -work ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/mentor/altera_xcvr_fpll_a10.sv"        -work ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/a10_avmm_h.sv"                         -work ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/alt_xcvr_native_avmm_nf.sv"            -work ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/mentor/a10_avmm_h.sv"                  -work ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/mentor/alt_xcvr_native_avmm_nf.sv"     -work ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/alt_xcvr_pll_embedded_debug.sv"        -work ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/alt_xcvr_pll_avmm_csr.sv"              -work ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_140/sim/mentor/alt_xcvr_pll_avmm_csr.sv"       -work ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140
+vcom     "$IP_DIR/ip_arria10_pll_xgmii_mac_clocks.vhd"                                                                                                 

libraries/technology/ip_arria10/pll_xgmii_mac_clocks/generate_ip.sh

+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014                                                        
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>           
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands                             
+#                                                                           
+# This program is free software: you can redistribute it and/or modify      
+# it under the terms of the GNU General Public License as published by      
+# the Free Software Foundation, either version 3 of the License, or         
+# (at your option) any later version.                                       
+#                                                                           
+# This program is distributed in the hope that it will be useful,           
+# but WITHOUT ANY WARRANTY; without even the implied warranty of            
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             
+# GNU General Public License for more details.                              
+#                                                                           
+# You should have received a copy of the GNU General Public License         
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.     
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+#   Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+#   ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_pll_xgmii_mac_clocks.qsys \
+              --synthesis=VHDL \
+              --simulation=VHDL \
+              --output-directory=generated \
+              --allow-mixed-language-simulation

libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg

+hdl_lib_name = ip_arria10_pll_xgmii_mac_clocks  
+hdl_library_clause_name = ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140
+hdl_lib_uses = 
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+modelsim_compile_ip_files =
+    $RADIOHDL/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
+
+synth_files =
+    
+test_bench_files = 
+
+quartus_qip_files =
+    generated/ip_arria10_pll_xgmii_mac_clocks.qip