Fixed expected statistics sim error by extending verification into next syn...

Fixed expected statistics sim error by extending verification into next syn interval using c_bsn_latency.

applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd

@@ -114,8 +114,8 @@
 --     sim:/tb_lofar2_unb2c_sdp_station_bf/sp_ssts_arr2 \
 --     sim:/tb_lofar2_unb2c_sdp_station_bf/bsts_arr2
 --   > run -a  
---   Takes about   40 m when g_read_all_* = FALSE
---   Takes about 1h 5 m when g_read_all_* = TRUE
+--   Takes about 1h  1 m when g_read_all_* = FALSE
+--   Takes about 1h 30 m when g_read_all_* = TRUE
 --
 -------------------------------------------------------------------------------
 LIBRARY IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, lofar2_unb2c_sdp_station_lib;
@@ -168,6 +168,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf IS
   CONSTANT c_node_nr             : NATURAL := 0;
   CONSTANT c_gn_index            : NATURAL := c_unb_nr * 4 + c_node_nr;           -- this node GN
   CONSTANT c_init_bsn            : NATURAL := 17;  -- some recognizable value >= 0
+  CONSTANT c_bsn_latency         : NATURAL := 5;  -- used to time stimuli_done
 
   CONSTANT c_id                  : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_gn_index, 8);
   CONSTANT c_version             : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
@@ -980,8 +981,9 @@ BEGIN
     ----------------------------------------------------------------------------
     -- Wait for enough WG data and start of sync interval
     ----------------------------------------------------------------------------
-    mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,                               -- read BSN low
-                            "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync*3,  -- this is the wait until condition
+    -- read BSN low, this is the wait until condition
+    mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+                            "UNSIGNED", rd_data, ">=", c_init_bsn + c_bsn_latency + c_nof_block_per_sync*3,
                             c_sdp_T_sub, tb_clk);
 
     -- Stimuli done, now verify results at end of test