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Commit 240c5751 authored by Job van Wee's avatar Job van Wee
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......@@ -18,12 +18,12 @@
--
-------------------------------------------------------------------------------
-- Author: Job van Wee
-- Purpose: Folding a stream of data into a mm data configuration so it can be
-- stored in a DDR RAM-stick.
-- Purpose: when there is output this component will turn it back into a
-- sosi arr.
--
-- Description:
-- First the data from the ddr memory gets resized into its original size
-- after that the data gets assigned a bsn.
-- The data from the ddr memory gets resized into its original size and gets
-- back its bsn.
--
-- Remark:
-- Use VHDL coding template from:
......
......@@ -18,11 +18,10 @@
--
-------------------------------------------------------------------------------
-- Author: Job van Wee
-- Purpose: Resize the input data vector so that the output data vector can be
-- stored into the ddr memory.
-- Purpose: Spread out the input sosi over a sosi array.
--
-- Description:
-- The input data gets resized and put into the output data vector.
-- The input sosi gets split up and spread out over the sosi array.
--
-- Remark:
-- Use VHDL coding template from:
......
......@@ -18,11 +18,13 @@
--
-------------------------------------------------------------------------------
-- Author: Job van Wee
-- Purpose: Resize the input data vector so that the output data vector can be
-- stored into the ddr memory.
-- Purpose: resize the data into a single sosi with a width of g_out_data_w.
--
-- Description:
-- The input data gets resized and put into the output data vector.
-- The data gets collected into a vector(c_v) and from this vector the output
-- data gets read. When the reading passes the halfway point of c_v new data
-- is requested and the whole vector shifts g_in_data_w amount of bits to fit
-- the new data at the end.
--
-- Remark:
-- Use VHDL coding template from:
......
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